{"title":"Blueprint for logic","authors":"J. Sordoillet, S. Davey","doi":"10.1049/ESS:20060308","DOIUrl":"https://doi.org/10.1049/ESS:20060308","url":null,"abstract":"Assertion languages in hardware description languages (HDLs) such as System Verilog and the Property Specification Language (PSL) can do a lot to improve the effectiveness of verification flows. Assertions give better local observability of the functionality they represent. Assertions augment textual specifications to provide a more formal, executable representation of the functionality. And, as the assertion languages have common semantics for both formal and simulation-based environments, they provide a path to enhancing current simulation flows with model-checking technology.","PeriodicalId":132835,"journal":{"name":"Electronic Systems and Software","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123152891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A new face for FPGA design","authors":"C. Edwards","doi":"10.1049/ESS:20060305","DOIUrl":"https://doi.org/10.1049/ESS:20060305","url":null,"abstract":"The second major change is coming in the way people design with field-programmable gate arrays (FPGAs). When they first appeared, most engineers used schematic diagrams to describe what the FPGA circuits should do. That then changed to hardware description languages (HDLs) such as Verilog and VHDL. These look more like software programs, although the code is generally structured very differently from algorithms described using software languages such as C. Now, C is emerging as a language that will take algorithms straight to hardware without involving either HDLs or schematics.","PeriodicalId":132835,"journal":{"name":"Electronic Systems and Software","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123682897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Tune analogue simulations for accuracy and speed","authors":"P. Raynaud, J. Oudinot","doi":"10.1049/ESS:20060302","DOIUrl":"https://doi.org/10.1049/ESS:20060302","url":null,"abstract":"Mixed-signal chips present the engineering team with a dilemma. Even if all the blocks, including the analogue blocks, have been validated separately, the result can be a failed chip. Verifying the interaction between blocks should be mandatory. But high device density means it is not practical to debug the silicon after manufacture. So design validation before tape-out is critical. The process of simulating a complete system-on-chip or system-in-package at transistor level has become impossible with traditional methodologies. It can take, when it does run, weeks or months for a single test, even with a fast Spice engine, due to capacity limitations and the limited potential for accuracy-versus-speed tradeoffs in analogue blocks. Taking into account parasitic effects makes the simulation problem worse. However, behavioural modelling offers a way forward.","PeriodicalId":132835,"journal":{"name":"Electronic Systems and Software","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127083692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Problems bubble up to the top","authors":"L. Collins","doi":"10.1049/ESS:20060306","DOIUrl":"https://doi.org/10.1049/ESS:20060306","url":null,"abstract":"One problem with future metal interconnect systems is that they may be too fragile to be reliable. The problem is the stress caused by thermal mismatch between a package and a chip's surface that occurs when the two are attached to each other by reflowing the solder bumps. This stress can cause cracking at the surface interface and can be transmitted into the interconnect stack, causing cracks at other interfaces, such as between the barrier layers protecting the copper lines and the dielectric material. Their research used finite-element analysis to derive the electric-field distribution and intensity in a dielectric film, given various pore sizes, shapes, and permittivities, and various interconnections of the pores. Once the field had been calculated, it was used to drive a Monte Carlo analysis of charge flow. The work showed that, when the permittivity of a pore is less than that of the matrix it is in, the electric field tends to be enhanced within it, accelerating local charge carriers. If pores join, they can create channels of high electric field that provide a conduction route that promotes dielectric breakdown. So porous dielectrics can sometimes be worse insulators than non-porous ones.","PeriodicalId":132835,"journal":{"name":"Electronic Systems and Software","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121884581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Cookie cutter collisions [monoculture industry]","authors":"L. Collins","doi":"10.1049/ESS:20060409","DOIUrl":"https://doi.org/10.1049/ESS:20060409","url":null,"abstract":"Are you the victim of a monoculture? Perhaps you bought a home DSL router, found its set-up software too impenetrable to get working, and replaced it with another brand only to find it had the same software from the same chip company. Or perhaps you've been comparing DVD players and have realised that, for less than #50, they're basically all the same. What's going on? Marketing types talk grandly about differentiation being the key to sales in technology. Yet, many products look the same and feel the same. Has the electronics business turned into clone creation?","PeriodicalId":132835,"journal":{"name":"Electronic Systems and Software","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125691958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Static control [source-code analysis]","authors":"A. Cothard","doi":"10.1049/ESS:20060406","DOIUrl":"https://doi.org/10.1049/ESS:20060406","url":null,"abstract":"Source-code analysis lets you pick up programming errors without running the software. Spotting errors early in the process is the cheapest and usually the easiest way of avoiding problems and project delays, as with any design and production process. The problem with software is that you have to have a lot of it ready before you can test it fully. But what if you could subject even individual modules to scrutiny without demanding that the code actually runs? This is where source code analysis (SCA) comes in.","PeriodicalId":132835,"journal":{"name":"Electronic Systems and Software","volume":"543 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123101518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Architecture and plurality","authors":"P. Marsh","doi":"10.1049/ess:20060405","DOIUrl":"https://doi.org/10.1049/ess:20060405","url":null,"abstract":"It's all over for uniprocessors. Future performance advances will rely on the industry's ability to exploit the parallel pipelines made available by single-chip multiprocessors. But making the most of the performance on offer is still a major challenge. Multicore processors are now a familiar to people buying desktop PCs and servers but they are fairly new to most embedded developers, even though some of the first implementations of multi-core architectures turned up in the embedded space. This looks set to change as parallelism becomes the only practical way to address future performance requirements.","PeriodicalId":132835,"journal":{"name":"Electronic Systems and Software","volume":"3 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113986037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Block party [system modelling]","authors":"A. Milik, A. Zytka","doi":"10.1049/ess:20060407","DOIUrl":"https://doi.org/10.1049/ess:20060407","url":null,"abstract":"Block-based design makes it possible to simulate designs using different types of tool. Some blocks can run high-level tools such as Matlab, with others running as hardware simulations. However, tying the different tools together presents problems. Matlab and Simulink are good for high-level modelling but they do not give you the information needed for deciding on the split between hardware and software in a design. Giving them a way of linking to hardware descriptions can overcome that and produce better designs. An important factor in system-level design is performance. The performance problem is, to a large extent, dependent on where you place the boundary between the hardware and the software parts of a design. This boundary is constrained by several factors such as power consumption or system performance. In order to achieve the best results, the partitioning process should be performed for different combinations of possible solutions.","PeriodicalId":132835,"journal":{"name":"Electronic Systems and Software","volume":"35 1-10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120932388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Let the power fall [portable device power management]","authors":"L. Collins","doi":"10.1049/ESS:20060304","DOIUrl":"https://doi.org/10.1049/ESS:20060304","url":null,"abstract":"Power management has become a major headache for designers. To try to stop the battery draining in a matter of minutes, large sections of a portable device need to be turned off or at least slowed down when they are not heavily used. Doing this effectively needs cooperation between the system functions and the power-management circuitry. But, right now, as there are few standards in place, this level of power management needs cooperation between the suppliers of system devices and those making the power components. Changes in battery chemistry will force alterations to the power circuits in portable systems.","PeriodicalId":132835,"journal":{"name":"Electronic Systems and Software","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124155589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On-chip bugs for debug","authors":"C. Edwards","doi":"10.1049/ess:20060301","DOIUrl":"https://doi.org/10.1049/ess:20060301","url":null,"abstract":"The moment a chip arrives back from the fab is always tense. Once the first piece of silicon is down on the board and things check out electrically the thing to do is work out whether it really is an advanced system-on-chip (SoC) or a silicon-and-glass sandwich. Conceptually, the process is similar to the trace buffers used on many embedded processors. They do not capture actual instructions but record whether branches were taken or not. A debugger takes the data out through a test port and then uses it to reconstruct what happened inside the processor and display the instruction trace to the developer. With logic debug, the problem is more complex as there are so many different types of signal on the chip - not just a stream of instructions. But Novas's Siloti tool will use the recorded data in a similar way and attempt to show which signals changed during a given period.","PeriodicalId":132835,"journal":{"name":"Electronic Systems and Software","volume":"165 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122983604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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