Tune analogue simulations for accuracy and speed

Abstract

Mixed-signal chips present the engineering team with a dilemma. Even if all the blocks, including the analogue blocks, have been validated separately, the result can be a failed chip. Verifying the interaction between blocks should be mandatory. But high device density means it is not practical to debug the silicon after manufacture. So design validation before tape-out is critical. The process of simulating a complete system-on-chip or system-in-package at transistor level has become impossible with traditional methodologies. It can take, when it does run, weeks or months for a single test, even with a fast Spice engine, due to capacity limitations and the limited potential for accuracy-versus-speed tradeoffs in analogue blocks. Taking into account parasitic effects makes the simulation problem worse. However, behavioural modelling offers a way forward.