{"title":"Performance study on implementation of DVB-S2 low density parity check codes on additive white Gaussian noise channel and Rayleigh fading channel","authors":"H. Hussien, K. Shehata, M. Khedr, S. Hareth","doi":"10.1109/ICEDSA.2012.6507791","DOIUrl":"https://doi.org/10.1109/ICEDSA.2012.6507791","url":null,"abstract":"Low density parity check (LDPC) codes are one of the best error correcting codes known to approach the Shannon limit. This paper examines the impact of different rates and code lengths of Log Belief Propagation LDPC algorithm on the performance of digital video broadcasting-satellite-second generation (DVB-S2) on both Additive white Gaussian Noise (AWGN) channel and Rayleigh fading channel, it also examines low complexity LDPC algorithm which is minimum sum LDPC algorithm for DVB-S2 with different numbers of iterations and simulating it on both channels using matlab targeting to chose the appropriate algorithm for the architecture of DVB-S2 to be implemented hierarchically on semi-parallel LDPC design Field Programmable Gate Array.","PeriodicalId":132198,"journal":{"name":"2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126681305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Hybrid conjugated polymer/quantum dots thin films for electronics application","authors":"F. H. Naning, S. Malik, F. L. Supian","doi":"10.1109/ICEDSA.2012.6507783","DOIUrl":"https://doi.org/10.1109/ICEDSA.2012.6507783","url":null,"abstract":"Thirteen layers of P3HT/stearic acid films have been deposited using angle lifting deposition technique onto ITO coated glass substrate at constant surface pressure. Gas exposure method was employed to embed semiconducting nanoparticles in the P3HT/SA matrixes. The isotherm of composite P3HT/SA shows a unique trend combination of small molecules of stearic acid and long chain polymer. UV-Vis result revealed the presence of CdS quantum dots in between P3HT/SA matrices. After subtracting the spectra before and after gas exposure, it was found that the CdS peak is at 420 nm, indicating the size of quantum dots created is around 4nm.","PeriodicalId":132198,"journal":{"name":"2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA)","volume":"196 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133835311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Very low bandgap voltage reference with high PSRR enhancement stage implemented in 90nm CMOS process technology for LDO application","authors":"K. R. Francisco, J. Hora","doi":"10.1109/ICEDSA.2012.6507800","DOIUrl":"https://doi.org/10.1109/ICEDSA.2012.6507800","url":null,"abstract":"A low voltage bandgap reference with a high power supply rejection ratio is implemented in TSMC 90nm 1P9M 3.3V CMOS Process Technology. This design can be applied to LDO voltage regulators particularly used in wireless devices and ADC's whose immunity to noise is an essential property. Its power supply rejection ratio is improved by an enhancement stage so as to achieve a high performance analog and digital system which is usually limited by the PSRR of the bandgap reference. The design operates within a range of 2.6 to 3.6 V and has very small temperature and supply sensitivities measuring 6 ppm/°C and 20μV/V, respectively. The circuit's current consumption is around 127.117 μA and produces an output voltage of 213.982 mV. The design's PSRR is 82.7 dB and it has a total chip core area of 0.0137 mm2.","PeriodicalId":132198,"journal":{"name":"2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115153660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. R. Basar, F. Malek, K. Juni, M. I. M. Saleh, M. S. Idris
{"title":"A low power 2.4-GHz current reuse VCO for low power miniaturized transceiver system","authors":"M. R. Basar, F. Malek, K. Juni, M. I. M. Saleh, M. S. Idris","doi":"10.1109/ICEDSA.2012.6507804","DOIUrl":"https://doi.org/10.1109/ICEDSA.2012.6507804","url":null,"abstract":"The explosive growth of short range wireless communication systems has lead to highly demand of compact radio frequency (RF) circuit with low power design. As voltage control oscillator (VCO) is the core block of RF systems, this paper presents a low power and highly miniaturized current reuse 2.45 GHz VCO. The proposed VCO is designed with the staking switch two series transistors using current reuse topology and inversion-mode of PMOS varactor tank. The proposed VCO consists a single on chip inductor and four MOS transistors that simplifies the VCO circuit and shrink the chip area remarkably. The proposed VCO is designed with 0.18-μm CMOS process. At 1.2 V DC supply, the proposed VCO draws only 315 μA current resulted to the VCO operate at ultra low power (0.38 mW). Over the tuning range the proposed VCO has the phase noise of -127 dBc/Hz at 1 MHz offset. In order to eliminate additional matching voltage circuit, the tuning voltage (Vtune) is kept similar to the DC voltage supply for 2.45 GHz ISM band applications. The performance of the proposed VCO show the excellent optimization for low power of compact transceiver system.","PeriodicalId":132198,"journal":{"name":"2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA)","volume":"125 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133557430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Z. Al Azim, N. Chowdhury, Iftikhar Ahmad Niaz, M. H. Alam, I. Ahmed, D. M. Quazi
{"title":"Self consistent simulation of C-V characterization and ballistic performance of double gate SOI flexible-FET incorporating QM effects","authors":"Z. Al Azim, N. Chowdhury, Iftikhar Ahmad Niaz, M. H. Alam, I. Ahmed, D. M. Quazi","doi":"10.1109/ICEDSA.2012.6507819","DOIUrl":"https://doi.org/10.1109/ICEDSA.2012.6507819","url":null,"abstract":"Capacitance-Voltage (C-V) & Ballistic Current-Voltage (I-V) characteristics of Double Gate (DG) Silicon-on-Insulator (SOI) Flexible FETs having sub 35nm dimensions are obtained by self-consistent method using coupled Schrodinger-Poisson solver taking into account the quantum mechanical effects. Although, ATLAS simulations to determine current and other short channel effects in this device have been demonstrated in recent literature, C-V & Ballistic I-V characterizations by using self-consistent method are yet to be reported. C-V characteristic of this device is investigated here with the variation of bottom gate voltage. The depletion to accumulation transition point (i.e. Threshold voltage) of the C-V curve should shift in the positive direction when the bottom gate is negatively biased and our simulation results validate this phenomenon. Ballistic performance of this device has also been studied with the variation of top gate voltage.","PeriodicalId":132198,"journal":{"name":"2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133379314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A study of SIP trunk security and challenges","authors":"A. Jaber, S. Manickam, S. Ramdas","doi":"10.1109/ICEDSA.2012.6507806","DOIUrl":"https://doi.org/10.1109/ICEDSA.2012.6507806","url":null,"abstract":"Several voice over internet protocol (VoIP) providers migrate to their services to session initiation protocol (SIP). SIP is a lightweight signaling protocol used to implement in wiled VoIP services. However, with the global spread of this service, we can see how VoIP is affected by the stealing of SIP trunk services. Thus, the VoIP Trade Company will exhaust it effort and income. Our survey shows how much SIP security is enforced when somebody cracks the SIP server, and looks for any VoIP process trunk IP to use the server as a legitimate user, or to try to harm the trunk by injecting it with a forged source code that will lead to a road map for the hacker. The latter will make it deny the server, or inject it with the SQL script effect to come with DDos attacks. Our study shows the interest of researchers and students on VoIP security. It also provides a road map between the hypotheses and implementation, particularly on how SIP is affected by the variety of attacks from the outside world and from inside the local network.","PeriodicalId":132198,"journal":{"name":"2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129392762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
V. Maheshwari, Anushree, S. Mazumdar, R. Kar, D. Mandal, A. Bhattacharjee
{"title":"2-π Crosstalk noise model for deep submicron VLSI global RC interconnects","authors":"V. Maheshwari, Anushree, S. Mazumdar, R. Kar, D. Mandal, A. Bhattacharjee","doi":"10.1109/ICEDSA.2012.6507803","DOIUrl":"https://doi.org/10.1109/ICEDSA.2012.6507803","url":null,"abstract":"Noise estimation and avoidance are becoming very important issues in today's high performance IC design. This paper presents a much improved, highly accurate and efficient noise model called 2-π model for the estimation of crosstalk noise. The proposed model incorporates all the physical properties including victim and aggressor drivers, distributed RC characteristics of interconnects and coupling locations of both victim and aggressor lines. Then with the help of this model, expressions for peak noise and noise width as well as sensitivity expressions to the various model parameters are calculated. We then use these sensitivity expressions to analyze and evaluate the effectiveness of various noise avoidance techniques for the reduction of this crosstalk noise.","PeriodicalId":132198,"journal":{"name":"2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126056156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A study of signed multipliers on FPGAs","authors":"Mohamed Aly, Ahmed Sayed","doi":"10.1109/ICEDSA.2012.6507811","DOIUrl":"https://doi.org/10.1109/ICEDSA.2012.6507811","url":null,"abstract":"Multiplication is an important fundamental operation that is critical in most signal and image processing applications. It is also essential for all types of wireless communications applications. We compare general multipliers from an architecture point of view, maximum clock frequency, latency, throughput, resource usage, as well as dynamic power consumption. We use a flopped combinational baseline multiplier for our comparison and we use the same FPGA platform to be fair in our analysis. We conclude that the regular approach of implying the use of DSP elements in the HDL code is not the best.","PeriodicalId":132198,"journal":{"name":"2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA)","volume":"13 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132639506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Electroluminescence and photoluminescence properties of porous silicon nanostructures with optimum etching time of photo-electrochemical anodization","authors":"M. A. Zubaidab, M. Rusop, S. Abdullah","doi":"10.1109/ICEDSA.2012.6507774","DOIUrl":"https://doi.org/10.1109/ICEDSA.2012.6507774","url":null,"abstract":"Porous silicon nanostructures (PSiNs) has attracted attention as a promising material for optoelectronics applications. For this experiment, we present measurements of photoluminescence and electroluminescence of PSiNs. The study of the electrical properties of this material due to its potential as a novel porous silicon based devices. Objective of this experiment is to determine the electroluminescence of PSiNs. PSiNs samples were prepared by photo-electrochemical anodization using p-type silicon substrate. For the formation of PSiNs, a fixed current density (J=20 mA/cm2), was applied for the variety of etching time (10, 20, 30, 40 and 50 minutes). The light emission can be observed at visible range. Effective EL spectrum will be observed with its maximum intensity at ~655 nm (sample of 30 minutes), which is similar to its PL spectrum at ~675 nm. PSiNs is very promising material for light-emitting diode (LED) application. Porous silicon nanostructures light-emitting diode (PSiNs-LED) will be future flat screen display devices and one of the high potential demands of devices.","PeriodicalId":132198,"journal":{"name":"2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130054414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"SASC: A hardware string alignment coprocessor for stereo correspondence","authors":"M. Vigliar, M. Fratello, L. Puglia, G. Raiconi","doi":"10.1109/ICEDSA.2012.6507816","DOIUrl":"https://doi.org/10.1109/ICEDSA.2012.6507816","url":null,"abstract":"In this paper a design scheme is proposed for a hardware co-processor that, starting from a pair of stereo images, computes the “disparity map” between them used to define corresponding points on the two images. The followed approach, based on Dynamic Programming, is that proposed in a recent paper and exploits the well known Needleman & Wunsch's string-alignment algorithm used in bioinformatics. The architecture, highly modular, was designed using Bluespec System Verilog development tool and is described in detail. Synthesis results are shown for several FPGA platforms and demonstrates that the processor can result sufficiently small to be embedded in a totally hardware stereo images processing chain. Performance obtained and reported at the end of the paper show that the processor can run fast enough to be employed in real time instances.","PeriodicalId":132198,"journal":{"name":"2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130099895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}