Very low bandgap voltage reference with high PSRR enhancement stage implemented in 90nm CMOS process technology for LDO application

Abstract

A low voltage bandgap reference with a high power supply rejection ratio is implemented in TSMC 90nm 1P9M 3.3V CMOS Process Technology. This design can be applied to LDO voltage regulators particularly used in wireless devices and ADC's whose immunity to noise is an essential property. Its power supply rejection ratio is improved by an enhancement stage so as to achieve a high performance analog and digital system which is usually limited by the PSRR of the bandgap reference. The design operates within a range of 2.6 to 3.6 V and has very small temperature and supply sensitivities measuring 6 ppm/°C and 20μV/V, respectively. The circuit's current consumption is around 127.117 μA and produces an output voltage of 213.982 mV. The design's PSRR is 82.7 dB and it has a total chip core area of 0.0137 mm2.