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Miniaturization of a UWB antenna with dual band-notched at WLAN/WiMAX frequency bands WLAN/WiMAX频段双陷波超宽带天线的小型化
2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA) Pub Date : 2012-12-01 DOI: 10.1109/ICEDSA.2012.6507778
E. Tammam, K. Yoshitomi, A. Allam, M. El-Sayed, H. Kanaya, K. Yoshida
{"title":"Miniaturization of a UWB antenna with dual band-notched at WLAN/WiMAX frequency bands","authors":"E. Tammam, K. Yoshitomi, A. Allam, M. El-Sayed, H. Kanaya, K. Yoshida","doi":"10.1109/ICEDSA.2012.6507778","DOIUrl":"https://doi.org/10.1109/ICEDSA.2012.6507778","url":null,"abstract":"In this paper, a highly compact symmetrical planar ultra-wideband (UWB) antenna with dual band-notched at the bands of the wireless local area network (WLAN) and worldwide interoperability for microwave access (WiMAX) is presented. The size of the antenna is strictly miniaturized both physically and electrically. The band notching of WLAN and WiMAX is achieved through the etching of two slots in the ground plane and the radiating patch respectively. Based on the symmetry of the antenna, additional size reduction is achieved by using only the half of the proposed antenna, while the antenna still does the same function except some minor changes in the band notching characteristics which can be optimized. The physical size of the antenna after reduction is 6.9×18 mm2 which represents an electrical size of O.07λ0X0.19λ0 at the lowest frequency of operation. The antenna is properly matched to 50-ohm input resistance over the frequency band from 3.2-12 GHz. However, the frequency bands 3.4-3.8 GHz and 5.2-5.8 GHz are notched to mitigate the interference with WiMAX and WLAN technologies. The performance of the proposed full size and reduced size antennas is compared showing that the reduced size antenna has the same performance of the full size antenna.","PeriodicalId":132198,"journal":{"name":"2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116029921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Gender classification based on human radiation frequencies of chakra points and brain regions 基于人类脉轮点和大脑区域辐射频率的性别分类
2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA) Pub Date : 2012-12-01 DOI: 10.1109/ICEDSA.2012.6507794
M. H. Haron, M. Taib, M. Ali, M. Yunus
{"title":"Gender classification based on human radiation frequencies of chakra points and brain regions","authors":"M. H. Haron, M. Taib, M. Ali, M. Yunus","doi":"10.1109/ICEDSA.2012.6507794","DOIUrl":"https://doi.org/10.1109/ICEDSA.2012.6507794","url":null,"abstract":"This paper discusses on gender classification using k-nearest neighbor technique based on human radiation frequencies of chakra points and brain regions. The data applied in this study have been collected from 34 samples consisting of 17 males and 17 females. Frequency counter has been used for capturing the radiation at all points and regions. K-nearest neighbor and k-fold cross validation techniques have been applied for classification and validation respectively. Three groups of points have been considered for classification and validation. Group 1 consists of seven chakra points and four brain regions, group two consists of three chakra points and group 3 consists of three chakra points and one brain region. The outcome of this study shows group 1 has the highest accuracy in gender prediction.","PeriodicalId":132198,"journal":{"name":"2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA)","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124086458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Contactless check-ins using implied locations: A NFC solution simplifying business to consumer interaction in location based services 使用隐含位置的非接触式签到:一种NFC解决方案，在基于位置的服务中简化了企业与消费者的交互
2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA) Pub Date : 2012-11-05 DOI: 10.1109/ICEDSA.2012.6507812
A. Nandwani, R. Edwards, P. Coulton
{"title":"Contactless check-ins using implied locations: A NFC solution simplifying business to consumer interaction in location based services","authors":"A. Nandwani, R. Edwards, P. Coulton","doi":"10.1109/ICEDSA.2012.6507812","DOIUrl":"https://doi.org/10.1109/ICEDSA.2012.6507812","url":null,"abstract":"There has been considerable focus on delivering location based services using Global Positioning Systems (GPS) in order to acquire user location details and enable over the air interactions or experiences. In this paper we present an alternative system, where the focus changes to the use of Implied Location Based Services (ILBS) using Near Field Communications (NFC) enabled phones and tags. The user has to physically be at a specific location in order to enable specific actions; allowing for a more intimate interaction as users physically interact with the NFC terminal. To illustrate the concept we present a RFID tag based check-in system using Social Networks as a means to determine and validate the user's location. We present a black box prototype and discuss the advantages, disadvantages and suitability of such a system for different use-cases. We argue how physical check-ins simplify the user experience and remove the need for technical competency, user hardware or awareness of positioning accuracy.","PeriodicalId":132198,"journal":{"name":"2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA)","volume":"94 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121008932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
On-chip capacitor low dropout voltage regulator implemented in 90nm CMOS technology process 采用90nm CMOS工艺实现片上电容低压差稳压器
2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA) Pub Date : 2012-11-01 DOI: 10.1109/ICEDSA.2012.6507802
I. S. V. Arancon, J. Hora
{"title":"On-chip capacitor low dropout voltage regulator implemented in 90nm CMOS technology process","authors":"I. S. V. Arancon, J. Hora","doi":"10.1109/ICEDSA.2012.6507802","DOIUrl":"https://doi.org/10.1109/ICEDSA.2012.6507802","url":null,"abstract":"A low dropout voltage regulator designed and implemented in 90nm 1P9M 3.3V CMOS technology process is presented in this paper. The design consists mainly of three stages, namely, error amplifier, efficiency boosting circuit and a power stage which utilized a power PMOS. Moreover, the design employs a solution to bulky external capacitors of the present low dropout voltage regulators with an on-chip capacitor. Compensation scheme is also used to provide fast transient and stability. Capacitors used on this design doesn't exceed 13pF, this allows the designer to easily integrate the compensation capacitors within the LDO chip. The designed LDO has an active area of 1.14μm2 and a ground current of 94.2μA and a dropout voltage of 250mV. The input voltage is ranged from 2-3.6 volts for loading current of 150mA and the output of 1.75 volts.","PeriodicalId":132198,"journal":{"name":"2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115437652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
DDTA and DDCCTA: New active elements for analog signal processing DDTA和DDCCTA:用于模拟信号处理的新型有源元件
2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA) Pub Date : 2012-11-01 DOI: 10.1109/ICEDSA.2012.6507784
M. Kumngern
{"title":"DDTA and DDCCTA: New active elements for analog signal processing","authors":"M. Kumngern","doi":"10.1109/ICEDSA.2012.6507784","DOIUrl":"https://doi.org/10.1109/ICEDSA.2012.6507784","url":null,"abstract":"This paper presents new active elements, namely the differential difference transconductance amplifier (DDTA) and differential difference current conveyor transconductance amplifier (DDCCTA). Unlike the previously reported papers, the active elements in this paper can be implemented by using either commercially available integrated circuits (ICs) (i.e. AD 844, LM 13600) or IC techniques (i.e. CMOS or bipolar technologies). By using these elements-based circuits, achieved circuits can be implemented both as discrete and IC forms. The workability of the proposed circuits is confirmed by PSPICE simulators.","PeriodicalId":132198,"journal":{"name":"2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA)","volume":"67 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113957301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A capacitor cross-coupled differential cascade low-noise amplifier 电容交叉耦合差分级联低噪声放大器
2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA) Pub Date : 2012-11-01 DOI: 10.1109/ICEDSA.2012.6507799
M. S. Khalili, M. Jalali
{"title":"A capacitor cross-coupled differential cascade low-noise amplifier","authors":"M. S. Khalili, M. Jalali","doi":"10.1109/ICEDSA.2012.6507799","DOIUrl":"https://doi.org/10.1109/ICEDSA.2012.6507799","url":null,"abstract":"A gm-boosting technique implemented by capacitor cross-coupling of common-gate devices in a differential cascode low-noise amplifier (LNA) is presented for improving the gain and noise figure (NF) without significant increase in current consumption. The conventional cascode LNA exhibits a relatively low performance at millimeter-wave frequencies due to carrier mobility limitations and device parasitic in the common-gate stage. A cascode LNA is designed in a 180 nm RF CMOS process at center frequency of 40 GHz. It achieves a gain of 8.8 dB and a NF of 4.2 dB while reverse isolation is better than -15 dB. The LNA circuit consumes 6.5 mW from a 1.8 V supply.","PeriodicalId":132198,"journal":{"name":"2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114721661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
The development of tiny encryption algorithm (TEA) crypto-core for mobile systems 移动系统微型加密算法(TEA)加密核的开发
2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA) Pub Date : 2012-11-01 DOI: 10.1109/ICEDSA.2012.6507813
Stephanie Ang Yee Hunn, Siti Zarina binti Md Naziri, Norina binti Idris
{"title":"The development of tiny encryption algorithm (TEA) crypto-core for mobile systems","authors":"Stephanie Ang Yee Hunn, Siti Zarina binti Md Naziri, Norina binti Idris","doi":"10.1109/ICEDSA.2012.6507813","DOIUrl":"https://doi.org/10.1109/ICEDSA.2012.6507813","url":null,"abstract":"In this paper, a cryptographic algorithm design called Tiny Encryption Algorithm (TEA) is proposed in order to minimize the memory footprint and maximize the speed. The design was targeted for embedded and mobile systems which concern more on speed and space. In TEA, the plaintext is encrypted and decrypted using the operations from mixed (orthogonal) algebraic groups and a huge number of rounds to achieve security with simplicity. At sixty-four (64) Feistel rounds, a total of 2,883 gates are used in the TEA encryption process with 16.72ns delay time while 2,805 gates are consumed in the decryption process with 14.78ns delay time. With these outcomes, the design is possible to be implemented on mobile devices which require considerable extent of security.","PeriodicalId":132198,"journal":{"name":"2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA)","volume":"769 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133005378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Design of an RF-DC conversion circuit for energy harvesting 用于能量收集的RF-DC转换电路的设计
2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA) Pub Date : 2012-11-01 DOI: 10.1109/ICEDSA.2012.6507787
K. Devi, M. D. Norashidah, C. Chakrabarty, S. Sadasivam
{"title":"Design of an RF-DC conversion circuit for energy harvesting","authors":"K. Devi, M. D. Norashidah, C. Chakrabarty, S. Sadasivam","doi":"10.1109/ICEDSA.2012.6507787","DOIUrl":"https://doi.org/10.1109/ICEDSA.2012.6507787","url":null,"abstract":"The design of voltage multiplier module used for energy harvesting system from ambient at downlink radio frequency range (935.2 MHz-959.8 MHz) of GSM-900 is presented. The function of this voltage multiplier circuit is to convert the RF energy signal into DC voltage that can be used to energize the low power electronic devices. The design was based on the Villard voltage multiplier circuit. A 4-stage Schottky diode voltage multiplier circuit was designed, modeled, simulated, fabricated and tested for its performance. Multisim was used for the modeling and simulation work. Simulation and practical tests were carried out for various input power levels at the specified frequency band. The RF input power levels verses the output voltages at the nodes of the Villard network were recorded. The input for the voltage multiplier module was fed through an efficient matching network from an RF energy harvesting antenna which is designed at 377 Ω impedance. For a received signal of -27dBm (1.99) μW at the antenna modules produce a DC output voltage of 2.1 V across 100 kΩ load.","PeriodicalId":132198,"journal":{"name":"2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132681982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
A low power, self-biased, bandwidth tracking semi-digital PLL design 一种低功耗、自偏置、带宽跟踪的半数字锁相环设计
2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA) Pub Date : 2012-11-01 DOI: 10.1109/ICEDSA.2012.6507782
M. Yogesh, M. Dietl, P. Sareen, K. Dewan
{"title":"A low power, self-biased, bandwidth tracking semi-digital PLL design","authors":"M. Yogesh, M. Dietl, P. Sareen, K. Dewan","doi":"10.1109/ICEDSA.2012.6507782","DOIUrl":"https://doi.org/10.1109/ICEDSA.2012.6507782","url":null,"abstract":"In a conventional charge-pump based PLL design, the loop parameters such as the bandwidth, jitter performance, charge-pump current, pull-in range among others govern the architecture and implementation details of the PLL. Different loop parameter specification change with a change in the reference frequency and in most cases, requires careful re-design of some of the PLL blocks. This paper describes the implementation of a semi-digital PLL for high bandwidth applications, which is self-biased, low-power and exhibits bandwidth tracking for all reference frequencies between 40 MHz and 2.5 GHz in 65nm CMOS technology. This design can be used for a wide range of reference frequencies without redesigning any block. The bandwidth can be fixed to some fraction of the reference frequency during design time. In this work, the PLL is designed to make the bandwidth track 1/20th of the reference frequency. Since this PLL is self-compensated, the PLL performance and the bandwidth remains the same over PVT corners.","PeriodicalId":132198,"journal":{"name":"2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114407562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Self-consistent C-V characterization of depletion mode buried channel InGaAs/InAs Quantum Well FET incorporating strain effects 考虑应变效应的损耗模式埋入沟道InGaAs/InAs量子阱场效应管的自一致C-V表征
2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA) Pub Date : 2012-11-01 DOI: 10.1109/ICEDSA.2012.6507820
I. Ahmed, I. Niaz, M. H. Alam, N. Chowdhury, Z. Azim, Q.D. Mohd Khosru
{"title":"Self-consistent C-V characterization of depletion mode buried channel InGaAs/InAs Quantum Well FET incorporating strain effects","authors":"I. Ahmed, I. Niaz, M. H. Alam, N. Chowdhury, Z. Azim, Q.D. Mohd Khosru","doi":"10.1109/ICEDSA.2012.6507820","DOIUrl":"https://doi.org/10.1109/ICEDSA.2012.6507820","url":null,"abstract":"We investigated Capacitance-Voltage (C-V) characteristics of the Depletion Mode Buried Channel InGaAs/InAs Quantum Well FET by using Self-Consistent method incorporating Quantum Mechanical (QM) effects. Though the experimental results of C-V for enhancement type device is available in recent literature, a complete characterization of electrostatic property of depletion type Buried Channel Quantum Well FET (QWFET) structure is yet to be done. C-V characteristics of the device is studied with the variation of three important process parameters: Indium (In) composition, gate dielectric and oxide thickness. We observed that inversion capacitance and ballistic current tend to increase with the increase in Indium (In) content in InGaAs barrier layer.","PeriodicalId":132198,"journal":{"name":"2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114970532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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