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2007 IEEE Custom Integrated Circuits Conference最新文献

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Analysis of Data Remanence in a 90nm FPGA 90nm FPGA的数据残留分析
2007 IEEE Custom Integrated Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/CICC.2007.4405689
Tim Tuan, T. Strader, S. Trimberger
{"title":"Analysis of Data Remanence in a 90nm FPGA","authors":"Tim Tuan, T. Strader, S. Trimberger","doi":"10.1109/CICC.2007.4405689","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405689","url":null,"abstract":"FPGAs are increasingly used in military applications, the security of a design when the part is powered off is an important property that needs to be analyzed. In this paper, we study data remanence in modern FPGAs using a custom 90nm FPGA designed for this test. The effects of temperatures, architecture, memory topology, and power off methods are analyzed. We find that different memory cells in the FPGA architecture have different remanence properties depending on their circuit design, data content, leakage and supply noise. To our knowledge, this is the first study of data remanence in FPGAs and in deep-submicron ICs.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120948499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A 1-V, 1.4-2.5 GHz Charge-Pump-Less PLL for a Phase Interpolator Based CDR 一种用于相位插补器CDR的1 v、1.4-2.5 GHz无电荷泵锁相环
2007 IEEE Custom Integrated Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/CICC.2007.4405733
Jaejin Park, J. Liu, L. Carley, C. Yue
{"title":"A 1-V, 1.4-2.5 GHz Charge-Pump-Less PLL for a Phase Interpolator Based CDR","authors":"Jaejin Park, J. Liu, L. Carley, C. Yue","doi":"10.1109/CICC.2007.4405733","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405733","url":null,"abstract":"A 1.4-2.5 GHz charge-pump-less phase locked loop (PLL) and a linear phase interpolator (PI) with dummy cells to enhance linearity are implemented in 0.13-mum CMOS. The loop filter with RC integrators and a V-I converter are proposed for achieving wide frequency range and high linearity in the voltage controlled oscillator (VCO) under a low supply voltage. The measured RMS and peak-peak jitters are 4.05 ps and 28.18 ps at 2 GHz, respectively. The measured DNL and INL of the PI are 0.27 LSB and 0.68 LSB, respectively.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133940382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST 基于65nm CMOS的1.0GHz多组嵌入式DRAM，具有并行刷新和分层BIST特性
2007 IEEE Custom Integrated Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/CICC.2007.4405849
D. Anand, J. Covino, J. Dreibelbis, J. Fifield, Kevin W. Gorman, M. Jacunski, Jake Paparelli, G. Pomichter, D. Pontius, M. Roberge, Stephen Sliva
{"title":"A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST","authors":"D. Anand, J. Covino, J. Dreibelbis, J. Fifield, Kevin W. Gorman, M. Jacunski, Jake Paparelli, G. Pomichter, D. Pontius, M. Roberge, Stephen Sliva","doi":"10.1109/CICC.2007.4405849","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405849","url":null,"abstract":"An embedded DRAM macro fabricated in 65 nm CMOS achieves 1.0 GHz multi-banked operation at 1.0 V yielding 584 Gbits/sec. The array utilizes a 0.1 1 mum2 cell with 20 fF deep trench capacitor and 2.2 nm gate oxide transfer gate. Concurrent refresh allows for high availability via a second bank address. At-speed test and repair is accomplished with a new hierarchical BIST architecture. Measured random cycle time exceeds 333 MHz at 1.0 V with functional operation from 750 mV to 1.5 V and densities up to 36.5 Mbits.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130094591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 0.5-V 16 GHz-20 GHz differential injection-locked divider in 0.18-μm CMOS process 0.5 v 16ghz - 20ghz差分注入锁定分频器，0.18 μm CMOS工艺
2007 IEEE Custom Integrated Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/CICC.2007.4405852
Hui Zheng, H. Luong
{"title":"A 0.5-V 16 GHz-20 GHz differential injection-locked divider in 0.18-μm CMOS process","authors":"Hui Zheng, H. Luong","doi":"10.1109/CICC.2007.4405852","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405852","url":null,"abstract":"An ultra-low-voltage (ULV) differential injection-locked (IL) divider topology is presented. By making use of a double-balanced active mixer with transformer feedback and a transformer-feedback VCO, the proposed ULV-IL divider features double-balanced differential-input differential-output, an ultra-low supply voltage comparable to the device threshold voltage, and low power consumption. Fabricated in a standard 0.18-μm CMOS process and operated at 0.5-V supply, the ULV-IL divider measures an input frequency range from 16.1 GHz to 20 GHz while consuming a total power from 2.75 mW to 4.35 mW. Moreover, two identical proposed ULV-IL dividers with differential inputs are implemented to achieve quadrature outputs with measured IQ sideband rejection of better than -35 dBc.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"172 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114844260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Wide Range Spatial Frequency Analysis of Intra-Die Variations with 4-mm 4000 × 1 Transistor Arrays in 90nm CMOS 90nm CMOS中4-mm 4000 × 1晶体管阵列模内变化的宽范围空间频率分析
2007 IEEE Custom Integrated Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/CICC.2007.4405727
D. Levacq, T. Minakawa, M. Takamiya, T. Sakurai
{"title":"A Wide Range Spatial Frequency Analysis of Intra-Die Variations with 4-mm 4000 × 1 Transistor Arrays in 90nm CMOS","authors":"D. Levacq, T. Minakawa, M. Takamiya, T. Sakurai","doi":"10.1109/CICC.2007.4405727","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405727","url":null,"abstract":"In order to investigate the systematic intra-die variations, the intra-die threshold voltage and on-current variations are measured thanks to 4-mm 4000times1 transistor arrays with 1 mum transistor-pitch in a 90 nm CMOS technology, achieving the widest spatial distribution range. The spatial frequency analysis of the variations indicates that both variations are random across 4 mm. The dependence of both variations on body bias is also measured and the relationships between threshold voltage variations and on-current variations are analyzed by using the alpha-power law model.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128511656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A Low-IF CMOS Simultaneous GPS Receiver Integrated in a Multimode Transceiver 集成在多模收发器中的低中频CMOS同步GPS接收机
2007 IEEE Custom Integrated Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/CICC.2007.4405692
Yang Xu, Kevin Wang, T. Pals, Aristotele Hadjichristos, K. Sahota, C. Persico
{"title":"A Low-IF CMOS Simultaneous GPS Receiver Integrated in a Multimode Transceiver","authors":"Yang Xu, Kevin Wang, T. Pals, Aristotele Hadjichristos, K. Sahota, C. Persico","doi":"10.1109/CICC.2007.4405692","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405692","url":null,"abstract":"This paper describes a GPS receiver circuit that operates simultaneously with WCDMA/CDMA2000 transceivers. This receiver uses a low-IF architecture to minimize the external passive components. The RF front-end circuit dynamically adjusts the linearity performance based on the instantaneous transmitting power of the integrated transmitter. The receiver measured performances are >80dB gain, 2.0dB noise figure, >20dB image rejection, maximum out-of-band IIP3 is +6dBm. The synthesize features -132dBc/Hz phase noise at 1MHz offset frequency and a total integrated double sideband phase noise of less than -30dBc in the 100Hz to 1MHz band. The receiver is fabricated in a 0.18 mum RFCMOS process, and draws 36.7mA at high linearity mode and 27.4mA at low linearity mode using switch mode power supply.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128580802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A Monolithic Bandpass Amplifier for Neural Signal Processing with 25-Hz Low-Frequency Cutoff 用于神经信号处理的25hz低频截止的单片带通放大器
2007 IEEE Custom Integrated Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/CICC.2007.4405707
P. Samsukha, S. Garverick
{"title":"A Monolithic Bandpass Amplifier for Neural Signal Processing with 25-Hz Low-Frequency Cutoff","authors":"P. Samsukha, S. Garverick","doi":"10.1109/CICC.2007.4405707","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405707","url":null,"abstract":"A monolithic bandpass amplifier for neural signal recording is reported. The low-frequency cutoff of the amplifier is obtained using low-gm feedback and a bias current of 500 pA to obtain a predictable response without off-chip components or calibration. The measured passband gain is 37.9 dB from 25 Hz to 15 kHz and input-referred noise is 1.04 muV rms, using a power consumption of 162 muW and a die area of 0.13 mm2 in 0.5-mum CMOS.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134015251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Power-Efficient Dual-Supply 64kB L1 Caches in a 65nm CMOS Technology 采用65nm CMOS技术的高效率双电源64kB L1高速缓存
2007 IEEE Custom Integrated Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/CICC.2007.4405834
Brian Campbell, J. Burnette, Naveen Javarappa, V. V. Kaenel
{"title":"Power-Efficient Dual-Supply 64kB L1 Caches in a 65nm CMOS Technology","authors":"Brian Campbell, J. Burnette, Naveen Javarappa, V. V. Kaenel","doi":"10.1109/CICC.2007.4405834","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405834","url":null,"abstract":"The 64 kB LI caches on the PA6T-1682M SoC CPU are composed of common data and tag structures fabricated in a 65 nm CMOS process and deliver a 1.5 cycle read latency with 32 GB/s bandwidth at 2 GHz. Several features optimize cache performance and power including power-down safe level shifters, streamlined dual-supply bitslices, fine-grain clock gating, and a centralized tag floorplan.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132841808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A Disturb Decoupled Column Select 8T SRAM Cell 干扰去耦柱选择8T SRAM单元
2007 IEEE Custom Integrated Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/CICC.2007.4405674
Vinod Ramadurai, R. Joshi, R. Kanj
{"title":"A Disturb Decoupled Column Select 8T SRAM Cell","authors":"Vinod Ramadurai, R. Joshi, R. Kanj","doi":"10.1109/CICC.2007.4405674","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405674","url":null,"abstract":"This paper presents a novel 8 transistor SRAM cell that can be used for enhancing cell Vddmin at and beyond 90 nm technology nodes. This cell provides a way to eliminate the column select read disturb scenario in SRAMs which is one of the impediments to lowering cell voltage. Read disturbs to the selected cell are then minimized by relying on a sense-amp based array architecture which enables discharging the bit-line (BL) capacitance to GND during a read operation thereby enhancing its low voltage operability. The sensitivity of the cell to BL height and sense timing has been studied and the feasibility of the cell has been proved by fabricating a 32 Kb array in a 90 nm PD/SOI technology. Hardware experiments and simulation results show improvements of cell Vddmin over traditional 6T cells by more than 150 mV for 90 nm PD/SOI technology.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129348728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
An X- and Ku-Band 8-Element Linear Phased Array Receiver X波段和ku波段8元线性相控阵接收机
2007 IEEE Custom Integrated Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/CICC.2007.4405841
Kwang-Jin Koh, Gabriel M. Rebeiz
{"title":"An X- and Ku-Band 8-Element Linear Phased Array Receiver","authors":"Kwang-Jin Koh, Gabriel M. Rebeiz","doi":"10.1109/CICC.2007.4405841","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405841","url":null,"abstract":"This paper presents an 8-element linear phased array receiver in 0.18-mum SiGe BiCMOS technology for X-and Ku-band applications. The array receiver adopts RF phase shifting architecture and the active 4-bit phase shifter synthesizes a phase by adding two properly weighted I-and Q-input. With all the digital control circuitry, bandgap reference and ESD protection for all I/O pads, the receiver consumes 170 mA from a 3.3 V supply voltage. The receiver shows about 20 dB of power gain per channel at 12 GHz with a 3-dB gain bandwidth from 8.5 to 14.5 GHz. The rms gain error is less than 0.9 dB and the rms phase error is less than 6deg at 6-18 GHz for all the 4-bit phase states. The minimum NF is 3.85 dB at 10-11 GHz and typical input PldB at 12 GHz is -31 dBm. The overall chip size is 2.2times2.45 mm2. To our knowledge, this is the first demonstration of an RF-based phased array in a silicon chip with the record rms phase and gain errors at 6-18 GHz.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122134416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
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