{"title":"一种用于相位插补器CDR的1 v、1.4-2.5 GHz无电荷泵锁相环","authors":"Jaejin Park, J. Liu, L. Carley, C. Yue","doi":"10.1109/CICC.2007.4405733","DOIUrl":null,"url":null,"abstract":"A 1.4-2.5 GHz charge-pump-less phase locked loop (PLL) and a linear phase interpolator (PI) with dummy cells to enhance linearity are implemented in 0.13-mum CMOS. The loop filter with RC integrators and a V-I converter are proposed for achieving wide frequency range and high linearity in the voltage controlled oscillator (VCO) under a low supply voltage. The measured RMS and peak-peak jitters are 4.05 ps and 28.18 ps at 2 GHz, respectively. The measured DNL and INL of the PI are 0.27 LSB and 0.68 LSB, respectively.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"A 1-V, 1.4-2.5 GHz Charge-Pump-Less PLL for a Phase Interpolator Based CDR\",\"authors\":\"Jaejin Park, J. Liu, L. Carley, C. Yue\",\"doi\":\"10.1109/CICC.2007.4405733\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 1.4-2.5 GHz charge-pump-less phase locked loop (PLL) and a linear phase interpolator (PI) with dummy cells to enhance linearity are implemented in 0.13-mum CMOS. The loop filter with RC integrators and a V-I converter are proposed for achieving wide frequency range and high linearity in the voltage controlled oscillator (VCO) under a low supply voltage. The measured RMS and peak-peak jitters are 4.05 ps and 28.18 ps at 2 GHz, respectively. The measured DNL and INL of the PI are 0.27 LSB and 0.68 LSB, respectively.\",\"PeriodicalId\":130106,\"journal\":{\"name\":\"2007 IEEE Custom Integrated Circuits Conference\",\"volume\":\"42 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE Custom Integrated Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2007.4405733\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2007.4405733","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11
摘要
在0.13 μ m CMOS中实现了1.4-2.5 GHz无电荷泵锁相环(PLL)和带假单元的线性相位插补器(PI)，以提高线性度。为了在低电源电压下实现压控振荡器(VCO)的宽频率范围和高线性度，提出了带RC积分器和V-I变换器的环路滤波器。测量到的RMS和峰值抖动在2ghz下分别为4.05 ps和28.18 ps。PI的DNL和INL分别为0.27 LSB和0.68 LSB。
A 1-V, 1.4-2.5 GHz Charge-Pump-Less PLL for a Phase Interpolator Based CDR
A 1.4-2.5 GHz charge-pump-less phase locked loop (PLL) and a linear phase interpolator (PI) with dummy cells to enhance linearity are implemented in 0.13-mum CMOS. The loop filter with RC integrators and a V-I converter are proposed for achieving wide frequency range and high linearity in the voltage controlled oscillator (VCO) under a low supply voltage. The measured RMS and peak-peak jitters are 4.05 ps and 28.18 ps at 2 GHz, respectively. The measured DNL and INL of the PI are 0.27 LSB and 0.68 LSB, respectively.
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