Brian Campbell, J. Burnette, Naveen Javarappa, V. V. Kaenel
{"title":"采用65nm CMOS技术的高效率双电源64kB L1高速缓存","authors":"Brian Campbell, J. Burnette, Naveen Javarappa, V. V. Kaenel","doi":"10.1109/CICC.2007.4405834","DOIUrl":null,"url":null,"abstract":"The 64 kB LI caches on the PA6T-1682M SoC CPU are composed of common data and tag structures fabricated in a 65 nm CMOS process and deliver a 1.5 cycle read latency with 32 GB/s bandwidth at 2 GHz. Several features optimize cache performance and power including power-down safe level shifters, streamlined dual-supply bitslices, fine-grain clock gating, and a centralized tag floorplan.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"46 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Power-Efficient Dual-Supply 64kB L1 Caches in a 65nm CMOS Technology\",\"authors\":\"Brian Campbell, J. Burnette, Naveen Javarappa, V. V. Kaenel\",\"doi\":\"10.1109/CICC.2007.4405834\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The 64 kB LI caches on the PA6T-1682M SoC CPU are composed of common data and tag structures fabricated in a 65 nm CMOS process and deliver a 1.5 cycle read latency with 32 GB/s bandwidth at 2 GHz. Several features optimize cache performance and power including power-down safe level shifters, streamlined dual-supply bitslices, fine-grain clock gating, and a centralized tag floorplan.\",\"PeriodicalId\":130106,\"journal\":{\"name\":\"2007 IEEE Custom Integrated Circuits Conference\",\"volume\":\"46 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE Custom Integrated Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2007.4405834\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2007.4405834","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Power-Efficient Dual-Supply 64kB L1 Caches in a 65nm CMOS Technology
The 64 kB LI caches on the PA6T-1682M SoC CPU are composed of common data and tag structures fabricated in a 65 nm CMOS process and deliver a 1.5 cycle read latency with 32 GB/s bandwidth at 2 GHz. Several features optimize cache performance and power including power-down safe level shifters, streamlined dual-supply bitslices, fine-grain clock gating, and a centralized tag floorplan.
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