2013 14th International Workshop on Microprocessor Test and Verification最新文献_第2页

Proving QBF-hardness in Bounded Model Checking for Incomplete Designs 不完全设计有界模型检验中qbf硬度的证明

2013 14th International Workshop on Microprocessor Test and Verification Pub Date : 2013-12-11 DOI: 10.1109/MTV.2013.11

Christian Miller, Christoph Scholl, B. Becker

{"title":"Proving QBF-hardness in Bounded Model Checking for Incomplete Designs","authors":"Christian Miller, Christoph Scholl, B. Becker","doi":"10.1109/MTV.2013.11","DOIUrl":"https://doi.org/10.1109/MTV.2013.11","url":null,"abstract":"Bounded Model Checking (BMC) is a major verification technique for finding errors in sequential circuits by unfolding the design iteratively and converting the BMC instances into Boolean satisfiability (SAT) formulas. Here, we consider incomplete designs (i.e. those containing so-called black boxes) where the verification task is to prove unrealizability of a property. A property is called unrealizable by an incomplete design, if there is an error which can not be compensated by any implementation of the black boxes. While 01X-modeling of the unknown behavior of the black boxes yields easy-to-solve SAT problems, the logic of quantified Boolean formulas (QBF) is needed for 01X-hard problems to obtain a more precise modeling. However, QBF-modeling does not guarantee success in proving unrealizability. To this purpose, we introduce the concept of QBF-hardness in this paper, a classification of problems for which the QBF-based modeling does not provide a result. Furthermore, we present an iterative method to prove the QBF-hardness. We provide a first practical example (a parameterized incomplete arbiter bus system) to demonstrate the concept.","PeriodicalId":129513,"journal":{"name":"2013 14th International Workshop on Microprocessor Test and Verification","volume":"149 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116750725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

IP Testing for Heterogeneous SOCs 异构soc的IP测试

2013 14th International Workshop on Microprocessor Test and Verification Pub Date : 2013-12-11 DOI: 10.1109/MTV.2013.19

Narendra Kamat

引用次数: 3

Hierarchical Verification Framework for Samsung Reconfigurable Processor Video System 三星可重构处理器视频系统的层次验证框架

2013 14th International Workshop on Microprocessor Test and Verification Pub Date : 2013-12-11 DOI: 10.1109/MTV.2013.18

Hoyoung Kim, Seonghun Jeong, Sunmin Kwon, Soojung Ryu

引用次数: 2

USB Validation Challenges on C45SOI & C28NM Technology Products 基于C45SOI的USB验证挑战C28NM技术产品

2013 14th International Workshop on Microprocessor Test and Verification Pub Date : 2013-12-11 DOI: 10.1109/MTV.2013.12

M. Pandey, Atul Gupta, Shwetank Shekhar

引用次数: 1

An Approach for In-House USB2.0 Electrical Compliance Testing on Nanoscale SoC 纳米级SoC内部USB2.0电气符合性测试方法

2013 14th International Workshop on Microprocessor Test and Verification Pub Date : 2013-12-11 DOI: 10.1109/MTV.2013.29

M. Pandey, Shwetank Shekhar, Nitin Saxena, G. Agarwal, Amersh Kumar

引用次数: 1

State Retention Validation of C66X DSP Core C66X DSP核心的状态保持验证

2013 14th International Workshop on Microprocessor Test and Verification Pub Date : 2013-12-11 DOI: 10.1109/MTV.2013.31

R. Venkatasubramanian, O. Olorode, A. Arun

引用次数: 0

Automatic Network Protocol Synthesis from UML Sequence Diagrams 从UML序列图中自动合成网络协议

2013 14th International Workshop on Microprocessor Test and Verification Pub Date : 2013-12-11 DOI: 10.1109/MTV.2013.21

E. Ebeid, F. Fummi, D. Quaglia, F. Stefanni

引用次数: 0

Measuring the Gain of Automatic Debug 自动调试增益的测量

2013 14th International Workshop on Microprocessor Test and Verification Pub Date : 2013-12-11 DOI: 10.1109/MTV.2013.17

Daniel Hansson, H. Uronen-Hansson

{"title":"Measuring the Gain of Automatic Debug","authors":"Daniel Hansson, H. Uronen-Hansson","doi":"10.1109/MTV.2013.17","DOIUrl":"https://doi.org/10.1109/MTV.2013.17","url":null,"abstract":"The purpose of regression testing is to quickly catch any deterioration in quality of a product under development. The more frequently tests are run, the earlier new issues can be detected resulting in a larger burden for the engineers who need to manually debug all test failures, many of which are failing due to the same underlying bug. However, there are software tools that automatically debug the test failures back to the faulty change and notifies the engineer who made this change. By analyzing data from a real commercial ASIC project we aimed to measure whether bugs are fixed faster when using automatic debug tools compared to manual debugging. All bugs in an ASIC development project were analyzed over a period of 3 months in order to determine the time it took the bug to be fixed and to compare the results from both automatic and manual debug. By measuring the time from when the bug report was sent out by the automatic debug tool until the bug was fixed, we can show that bugs are fixed 4 times faster with automatic debug enabled. Bug fixing time was on average 5.7 hours with automatic debug and 23.0 hours for manual debug. The result was achieved by comparing bugs that were automatically debugged to those issues that could not be debugged by the tool, because those issues were outside the defined scope of the device under test. Such issues are still reported by the automatic debug tool but marked as requiring manual debug and is consequently a good point of comparison. A 4 times quicker bug fixing process is significant and can ultimately contribute to a shortening of a development project as the bug turnaround time is one of the key aspects defining the length of a project, especially in the later phase just before release.","PeriodicalId":129513,"journal":{"name":"2013 14th International Workshop on Microprocessor Test and Verification","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125454595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Target Environment Simulation and its Impact on Architecture Validation: A Case Study of Thread-Level Speculative Execution 目标环境仿真及其对体系结构验证的影响:以线程级推测执行为例

2013 14th International Workshop on Microprocessor Test and Verification Pub Date : 2013-12-11 DOI: 10.1109/MTV.2013.27

Jack L. Mason, G. Simco

引用次数: 0

On the Functional Test of the Register Forwarding and Pipeline Interlocking Unit in Pipelined Processors 流水线处理器中寄存器转发和流水线联锁单元的功能测试

2013 14th International Workshop on Microprocessor Test and Verification Pub Date : 2013-12-11 DOI: 10.1109/MTV.2013.10

P. Bernardi, R. Cantoro, Lyl M. Ciganda Brasca, B. Du, E. Sánchez, M. Reorda, M. Grosso, O. Ballan

{"title":"On the Functional Test of the Register Forwarding and Pipeline Interlocking Unit in Pipelined Processors","authors":"P. Bernardi, R. Cantoro, Lyl M. Ciganda Brasca, B. Du, E. Sánchez, M. Reorda, M. Grosso, O. Ballan","doi":"10.1109/MTV.2013.10","DOIUrl":"https://doi.org/10.1109/MTV.2013.10","url":null,"abstract":"When the result of a previous instruction is needed in the pipeline before it is available, a “data hazard” occurs. Register Forwarding and Pipeline Interlock (RF&PI) are mechanisms suitable to avoid data corruption and to limit the performance penalty caused by data hazards in pipelined microprocessors. Data hazards handling is part of the microprocessor control logic; its test can hardly be achieved with a functional approach, unless a specific test algorithm is adopted. In this paper we analyze the causes for the low functional testability of the RF&PI logic and propose some techniques able to effectively perform its test. In particular, we describe a strategy to perform Software-Based Self-Test (SBST) on the RF&PI unit. The general structure of the unit is analyzed, a suitable test algorithm is proposed and the strategy to observe the test responses is explained. The method can be exploited for test both at the end of manufacturing and in the operational phase. Feasibility and effectiveness of the proposed approach are demonstrated on both an academic MIPS-like processor and an industrial System-on-Chip based on the Power Architecture™.","PeriodicalId":129513,"journal":{"name":"2013 14th International Workshop on Microprocessor Test and Verification","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121376462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20