IP Testing for Heterogeneous SOCs

Abstract

The verification methodology world has progressed spectacularly during the last decade, with increasingly sophisticated techniques and frameworks for driving test stimulus into the device under test. Frequently, however, the focus of these methodology improvements is IP-level verification (i.e., just one part of an overall system or SOC). The last few generations of AMD products combined multi-core CPUs and several multi-media IP blocks such as graphics, video decode, display, and memory-I/O interconnect paths into highly complex heterogeneous SOCs, culminating in the first implementation of the Heterogeneous System Architecture (HSA). Based on our experience with these SOCs, we observe that verification at the SOC level presents a unique set of requirements, challenges, and opportunities. This paper takes a retrospective look at the evolution of and experience with running IP (in particular, graphics) test stimulus on the last three generations of heterogeneous SOCs.