{"title":"Analyzing Efficacy of Constrained Test Program Generators - A Case Study","authors":"Vinayak Kamath, Farhan Rahman, Li-C. Wang","doi":"10.1109/MTV.2013.30","DOIUrl":"https://doi.org/10.1109/MTV.2013.30","url":null,"abstract":"Functional verification of microprocessor designs exposes bugs in the design implementation by using a vast suite of randomly generated and directed test programs. Typically, more than one random test program generator(exerciser) is used. Our objective here is to develop a methodology to assess exerciser verification efficiency qualitatively and quantitatively. This understanding is used to identify untested design properties and fix coverage holes. We demonstrate this using a comparative analysis of the abilities of two in-house exercisers based to verify secure virtual mode(SVM) functionalities of an x86 instruction set architecture-based microprocessor core. We demonstrate that simulation data can be used to provide feedback on verification completeness to increase functional coverage.","PeriodicalId":129513,"journal":{"name":"2013 14th International Workshop on Microprocessor Test and Verification","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129630711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Anti-counterfeit Techniques: From Design to Resign","authors":"Ujjwal Guin, Domenic Forte, M. Tehranipoor","doi":"10.1109/MTV.2013.28","DOIUrl":"https://doi.org/10.1109/MTV.2013.28","url":null,"abstract":"The emerging threat of counterfeit electronic components has become a major challenge over the past decade. To address this growing concern, a suite of tests for the detection of such parts has been created. However, due to the large test time and cost, it is fairly difficult to implement them. Moreover, the presence of different types of counterfeits in the supply chain - recycled, remarked, overproduced, out-of-spec/defective, cloned, forged documentation, and tampered - makes the detection even more challenging. In this paper, we present a detailed taxonomy of counterfeit types to analyze the vulnerabilities in the electronic component supply chain. We then present the state of knowledge on anti-counterfeit technologies to help prevent counterfeit components from ever entering into the supply chain and to provide capabilities for easy detection.","PeriodicalId":129513,"journal":{"name":"2013 14th International Workshop on Microprocessor Test and Verification","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130790691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Functional Validation of a New Network Switch Architecture Using Rapid Prototyping Techniques","authors":"B. Kahne, J. Holt","doi":"10.1109/MTV.2013.15","DOIUrl":"https://doi.org/10.1109/MTV.2013.15","url":null,"abstract":"When developing a new architecture with a new programming model, not only must performance be taken into account, but the programming model itself must also be validated, in order to ensure that software will run correctly and with sufficient efficiency. In this paper, we describe how we applied rapid prototyping techniques to model a new network switch architecture. By concentrating on functional modeling and using a high-level description for core modeling, as well as abstract C++ models for peripherals, our model was able to track the specification, allowing studies to be performed on code density and ABI requirements, with sufficient time to be able to influence the architecture as it evolved.","PeriodicalId":129513,"journal":{"name":"2013 14th International Workshop on Microprocessor Test and Verification","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127638095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
David Brier, R. Venkatasubramanian, Sowmya Rangarajan, A. Arun, D. Thompson, Neelima Muralidharan
{"title":"Verification Methodology of Heterogeneous DSP+ARM Multicore Processors for Multi-core System on Chip","authors":"David Brier, R. Venkatasubramanian, Sowmya Rangarajan, A. Arun, D. Thompson, Neelima Muralidharan","doi":"10.1109/MTV.2013.32","DOIUrl":"https://doi.org/10.1109/MTV.2013.32","url":null,"abstract":"Processor complexity continues to evolve, with new architectures more complex and more tightly intertwined with the systems in which they operate than previous generations. Magnifying the individual processor complexity is the need to create heterogeneous processor clusters which contain multiple heterogeneous processors (ARM and DSP) with multiple levels of caches. These processor clusters need to be validated for functionality and memory coherency across all the levels of caches. Management of the verification process of these processor cluster has likewise grown in complexity impacting the creation and management of tests, of particular interest are the C and assembly code driven tests which are the primary methods addressed in this paper. Lessons in test creation from the UVM, software coding and other previous test management methods are combined to permit automation of testing for generation of test suites for processor sub-systems. Key elements of these methodologies are detailed in this paper.","PeriodicalId":129513,"journal":{"name":"2013 14th International Workshop on Microprocessor Test and Verification","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123130405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An Approach to Multi-core Functional Gate-Level Simulation Minimizing Synchronization and Communication Overheads","authors":"T. B. Ahmad, M. Ciesielski","doi":"10.1109/MTV.2013.20","DOIUrl":"https://doi.org/10.1109/MTV.2013.20","url":null,"abstract":"This paper addresses performance issues encountered in parallel functional gate-level simulation executed on multi-core machine. It demonstrates that a straightforward application of the multi-core simulation on a multi-core machine does not improve simulation performance. This is due to unbalanced partitioning, lack of sufficient concurrency in the design partitions, overhead due to communication between partitions, and synchronization overhead imposed by the simulator. We propose, implement and automate a generic (partitioning-independent) prediction-based solution to eliminate or minimize communication and synchronization overhead in an event-driven functional gate-level simulation on a multi-core machine. We demonstrate speedup obtained with this method on a set of real Opensource designs.","PeriodicalId":129513,"journal":{"name":"2013 14th International Workshop on Microprocessor Test and Verification","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128864009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Basu, P. Mishra, Priyadarsan Patra, Amir Nahir, Allon Adir
{"title":"Dynamic Selection of Trace Signals for Post-Silicon Debug","authors":"K. Basu, P. Mishra, Priyadarsan Patra, Amir Nahir, Allon Adir","doi":"10.1109/MTV.2013.13","DOIUrl":"https://doi.org/10.1109/MTV.2013.13","url":null,"abstract":"Post-silicon validation is one of the most expensive and complex tasks in today's System-on-Chip (SoC) design methodology. A major challenge in post-silicon debug is limited observability of the internal signals. Existing approaches address this issue by selecting a small set of useful signals. These signal states are stored in an on-chip trace buffer during execution. The applicability of existing methods is limited to a specific debug scenario where every component has equal importance all the time. In reality, a verification engineer would like to focus on a specific set of components (functional regions). Some regions can be ignored in a certain duration during execution due to clock gating and other considerations. Similarly, certain regions may be well verified datapath and less likely to have errors compared to other control-intensive regions. In this paper, we propose an efficient signal selection algorithm and a low-overhead trace controller design that would enable verification engineers to dynamically select a set of trace signals for improved error detection. Our experimental results using both ISCAS'89 benchmarks and Opencores circuits demonstrate that our approach can detect up to 3 times more errors compared to existing techniques.","PeriodicalId":129513,"journal":{"name":"2013 14th International Workshop on Microprocessor Test and Verification","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115264410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Ultra-Fast DMAC TLM Model for High Speed Virtual Platform Simulation","authors":"M. Safar, M. El-Moursy, A. Salem","doi":"10.1109/MTV.2013.14","DOIUrl":"https://doi.org/10.1109/MTV.2013.14","url":null,"abstract":"Granularity of transactions, which are initiated by the Programmer's View (PV) models, has high impact on the simulation speed of Virtual Platforms (VP). Since PV models are intended to run at high simulation speed, hardware parameters such as data bus width should not slow-down the simulation speed of the PV-level abstracted transactions. Hardware parameters should be taken into account only to tune the Approximately-Timed (AT) models of the device. A new SystemC-TLM Direct Memory Access Controller (DMAC) model, for ARM PL080 is developed and validated. The programmed transfers are performed with coarse granularity for read/write transactions. QEMU-based and SystemC-TLM-based platforms are also implemented to determine the effect of the granularity of the transactions on the PV simulation speed. The developed model is compared with the existing ARM Fast Model and the open-source QEMU model. Up to 100x reduction in simulation time is achieved with the developed model.","PeriodicalId":129513,"journal":{"name":"2013 14th International Workshop on Microprocessor Test and Verification","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128320423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Modified Condition Decision Coverage: A Hardware Verification Perspective","authors":"Mohamed A. Salem, K. Eder","doi":"10.1109/MTV.2013.16","DOIUrl":"https://doi.org/10.1109/MTV.2013.16","url":null,"abstract":"Verification is a critical phase of the development cycle. It confirms the compliance of a design implementation with its functional specification. Coverage measures the progress of the verification plan. Structural coverage determines the code exercised by the functional tests. Modified Condition Decision Coverage (MC/DC) is a structural coverage type. This paper compiles a comprehensive overview of established MC/DC conventions, and develops novel MC/DC insights through conduction of experimental study for MC/DC in hardware verification. It provides a generic MC/DC overview while explaining MC/DC types, and criteria of MC/DC validation in the software domain. It introduces the motivation for adoption of MC/DC as a potential structural coverage type for hardware verification. The paper presents the experimental evaluation conducted over a diverse base of logic combinations. The introduced experimental results inferred distinct MC/DC insights. These insights present novel MC/DC aspects that optimize the minimal MC/DC coverage requirements, defines MC/DC compositionality concepts, and provide RTL design guidelines for MC/DC fulfillment.","PeriodicalId":129513,"journal":{"name":"2013 14th International Workshop on Microprocessor Test and Verification","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125126193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Practical Security Validation","authors":"M. King","doi":"10.1109/MTV.2013.23","DOIUrl":"https://doi.org/10.1109/MTV.2013.23","url":null,"abstract":"Attackers are increasingly making use of unintended hardware or firmware behavior to build exploits. To minimize the likelihood of these attacks and to meet their security objectives, hardware products are adopting secure development processes, including performing security validation of components critical to enforcing these objectives. Despite the increasing visibility of hardware security issues, in some cases lack of expertise can create challenges. When that is true, validation might need to be performed by people without deep security expertise. In those cases, validators should focus on tests and methodologies that do not require substantial training to deploy in order to provide a basic level of security coverage. Many issues in access control and cryptographic logic can be caught by targeting a small number of common mistakes. Testing of non-standard configurations stresses assumptions made by critical protocols and components. And commonly used methods like constrained random testing can be adapted to mimic techniques used by attackers to find exploitable vulnerabilities. When combined these strategies can reduce the need for explicit, testable security requirements and enable nearly all validators to uncover a wide range of potential vulnerabilities.","PeriodicalId":129513,"journal":{"name":"2013 14th International Workshop on Microprocessor Test and Verification","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129041622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Secure and Trusted SoC: Challenges and Emerging Solutions","authors":"A. Basak, Sanchita Mal-Sarkar, S. Bhunia","doi":"10.1109/MTV.2013.24","DOIUrl":"https://doi.org/10.1109/MTV.2013.24","url":null,"abstract":"Over the ages, hardware components, platforms and supply chains have been considered secure and trustworthy. However, recent discoveries and reports on security vulnerabilities and attacks in microchips and circuits violate this hardware root of trust. System-on-Chip (SoC) design based on reusable hardware intellectual property (IP) is now a pervasive design practice in the industry due to the dramatic reduction in design/verification cost and time. This growing reliance on reusable pre-verified hardware IPs and a wide array of design automation tools during SoC design, often acquired from untrusted 3rd party vendors, coupled with fabrication in untrusted offshore foundries severely affects the security and trustworthiness of SoCs used in diverse applications. This paper presents an overview of the various security challenges in the SoC design cycle and possible solutions for protection.","PeriodicalId":129513,"journal":{"name":"2013 14th International Workshop on Microprocessor Test and Verification","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130937000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}