Analyzing Efficacy of Constrained Test Program Generators - A Case Study

Abstract

Functional verification of microprocessor designs exposes bugs in the design implementation by using a vast suite of randomly generated and directed test programs. Typically, more than one random test program generator(exerciser) is used. Our objective here is to develop a methodology to assess exerciser verification efficiency qualitatively and quantitatively. This understanding is used to identify untested design properties and fix coverage holes. We demonstrate this using a comparative analysis of the abilities of two in-house exercisers based to verify secure virtual mode(SVM) functionalities of an x86 instruction set architecture-based microprocessor core. We demonstrate that simulation data can be used to provide feedback on verification completeness to increase functional coverage.