State Retention Validation of C66X DSP Core

Abstract

Low power design has become an important design requirement in any deep-submicron CMOS design development. State retention using retention flip flops is one of the low power techniques that offer the ability to save and restore the state of the design during a period of inactivity (IDLE or STANDBY mode). Since processor cores typically have a well-defined period of operation and inactivity, the state retention scheme is well suited for processor designs. This paper provides an overview of the various state retention implementation choices for processor cores and explains the state retention validation methodology for the different implementations. The state retention and validation methodology deployed for the TI C66x Core is explained in detail.