{"title":"目标环境仿真及其对体系结构验证的影响:以线程级推测执行为例","authors":"Jack L. Mason, G. Simco","doi":"10.1109/MTV.2013.27","DOIUrl":null,"url":null,"abstract":"Due to simulation overhead, validation of proposed microarchitecture enhancements may be limited to simple test scenarios, which focus on the known architectural deficiencies. These test scenarios often avoid a complete simulation of the eventual target environment in which the enhancements will be employed. A case study is presented, comparing and contrasting the performance of previous Thread-Level Speculation (TLS) proposals with that of a new, context-preserving proposal. Validation is performed within the constraints of a simulated target environment.","PeriodicalId":129513,"journal":{"name":"2013 14th International Workshop on Microprocessor Test and Verification","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Target Environment Simulation and its Impact on Architecture Validation: A Case Study of Thread-Level Speculative Execution\",\"authors\":\"Jack L. Mason, G. Simco\",\"doi\":\"10.1109/MTV.2013.27\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Due to simulation overhead, validation of proposed microarchitecture enhancements may be limited to simple test scenarios, which focus on the known architectural deficiencies. These test scenarios often avoid a complete simulation of the eventual target environment in which the enhancements will be employed. A case study is presented, comparing and contrasting the performance of previous Thread-Level Speculation (TLS) proposals with that of a new, context-preserving proposal. Validation is performed within the constraints of a simulated target environment.\",\"PeriodicalId\":129513,\"journal\":{\"name\":\"2013 14th International Workshop on Microprocessor Test and Verification\",\"volume\":\"24 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-12-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 14th International Workshop on Microprocessor Test and Verification\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MTV.2013.27\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 14th International Workshop on Microprocessor Test and Verification","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MTV.2013.27","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Target Environment Simulation and its Impact on Architecture Validation: A Case Study of Thread-Level Speculative Execution
Due to simulation overhead, validation of proposed microarchitecture enhancements may be limited to simple test scenarios, which focus on the known architectural deficiencies. These test scenarios often avoid a complete simulation of the eventual target environment in which the enhancements will be employed. A case study is presented, comparing and contrasting the performance of previous Thread-Level Speculation (TLS) proposals with that of a new, context-preserving proposal. Validation is performed within the constraints of a simulated target environment.