An Approach for In-House USB2.0 Electrical Compliance Testing on Nanoscale SoC

2013 14th International Workshop on Microprocessor Test and Verification Pub Date : 2013-12-11 DOI:10.1109/MTV.2013.29

M. Pandey, Shwetank Shekhar, Nitin Saxena, G. Agarwal, Amersh Kumar

{"title":"An Approach for In-House USB2.0 Electrical Compliance Testing on Nanoscale SoC","authors":"M. Pandey, Shwetank Shekhar, Nitin Saxena, G. Agarwal, Amersh Kumar","doi":"10.1109/MTV.2013.29","DOIUrl":null,"url":null,"abstract":"In today's era SOC manufacturers cannot imagine a product without USB, irrespective of domain i.e. networking automotive, cellular etc. The performance of USB depends fundamentally on the electrical characteristics. USB Implementers Forum (USB-IF) describes the mandatory Electrical compliance tests for certification of USB product. Moreover this gives an extra level of confidence to use the USB product. In legacy method, USB compliance testing is performed on a complete embedded product consisting of software/firmware, controller and USB PHY. In case of any issue or failure, it becomes very hard to isolate the source of problem. That's why there is need of an approach which can perform compliance testing isolating all the three entity and having sufficient debug capabilities to root cause the issues. This paper explains the reason for opting JTAG based approach for performing all the USB electrical compliance testing prescribed by USB-IF. This approach provides additional debugging capabilities to debug issues at low level.","PeriodicalId":129513,"journal":{"name":"2013 14th International Workshop on Microprocessor Test and Verification","volume":"261 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 14th International Workshop on Microprocessor Test and Verification","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MTV.2013.29","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

Abstract

In today's era SOC manufacturers cannot imagine a product without USB, irrespective of domain i.e. networking automotive, cellular etc. The performance of USB depends fundamentally on the electrical characteristics. USB Implementers Forum (USB-IF) describes the mandatory Electrical compliance tests for certification of USB product. Moreover this gives an extra level of confidence to use the USB product. In legacy method, USB compliance testing is performed on a complete embedded product consisting of software/firmware, controller and USB PHY. In case of any issue or failure, it becomes very hard to isolate the source of problem. That's why there is need of an approach which can perform compliance testing isolating all the three entity and having sufficient debug capabilities to root cause the issues. This paper explains the reason for opting JTAG based approach for performing all the USB electrical compliance testing prescribed by USB-IF. This approach provides additional debugging capabilities to debug issues at low level.

查看原文本刊更多论文

纳米级SoC内部USB2.0电气符合性测试方法

在当今时代，SOC制造商无法想象没有USB的产品，无论其领域是网络汽车，蜂窝等。USB的性能从根本上取决于其电气特性。USB实现者论坛(USB- if)介绍了USB产品认证的强制性电气符合性测试。此外，这为使用USB产品提供了额外的信心。在传统方法中，USB符合性测试是在由软件/固件，控制器和USB PHY组成的完整嵌入式产品上执行的。在任何问题或失败的情况下，很难隔离问题的根源。这就是为什么需要一种方法，它可以执行合规性测试，隔离所有三个实体，并具有足够的调试功能，以从根本上解决问题。本文解释了选择基于JTAG的方法执行USB- if规定的所有USB电气符合性测试的原因。这种方法提供了额外的调试功能，可以在较低的级别上调试问题。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

2013 14th International Workshop on Microprocessor Test and Verification

自引率

0.00%

发文量