International Symposium on Quality Electronic Design (ISQED)最新文献_第3页

Evaluation of tunnel FET-based flip-flop designs for low power, high performance applications 基于隧道场效应晶体管的低功耗高性能触发器设计评估

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523647

M. Cotter, Huichu Liu, S. Datta, N. Vijaykrishnan

引用次数: 23

Framework for analog test coverage 模拟测试覆盖的框架

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523653

D. Bhatta, I. Mukhopadhyay, S. Natarajan, P. Goteti, Bin Xue

引用次数: 9

Reliability-aware and energy-efficient synthesis of NoC based MPSoCs 基于NoC的mpsoc的可靠性感知和节能合成

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523678

Yong Zou, S. Pasricha

{"title":"Reliability-aware and energy-efficient synthesis of NoC based MPSoCs","authors":"Yong Zou, S. Pasricha","doi":"10.1109/ISQED.2013.6523678","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523678","url":null,"abstract":"In sub-65nm CMOS process technologies, networks-on-chip (NoC) are increasingly susceptible to transient faults (i.e., soft errors). To achieve fault tolerance, Triple Modular Redundancy (TMR) and Hamming Error Correction Codes (HECC) are often employed by designers to protect buffers used in NoC components. However, these mechanisms to achieve fault resilience introduce power dissipation overheads that can disrupt stringent chip power budgets and thermal constraints. In this paper, we propose a novel design-time framework (RESYN) to trade-off energy consumption and reliability in the NoC fabric at the system level for MPSoCs. RESYN employs a nested evolutionary algorithm approach to guide the mapping of cores on a die, and opportunistically determine locations to insert fault tolerance mechanisms in the NoC to minimize energy while satisfying reliability constraints. Our experimental results show that RESYN can reduce energy costs by 14.5% on average compared to a fully protected NoC, while still maintaining more than a 90% fault tolerance. If higher levels of reliability are desired, RESYN can generate a Pareto set of solutions allowing designers to select the most energy-efficient solution for any reliability goal. Given the increasing importance of reliability in the nanometer era for MPSoCs, this work provides important perspectives that can guide the reduction of overheads of reliable NoC design.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130955895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Manufacturable nanometer designs using standard cells with regular layout 可制造的纳米设计使用标准电池与规则布局

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523642

K. Subramaniyan, P. Larsson-Edefors

引用次数: 4

Low power sensor for temperature compensation in molecular biosensing 分子生物传感中用于温度补偿的低功耗传感器

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523644

D. Venuto

引用次数: 0

CPDI: Cross-power-domain interface circuit design in monolithic 3D technology 单片三维技术中的跨功率域接口电路设计

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523649

Jing Xie, Yang Du, Yuan Xie

引用次数: 1

Improving timing error tolerance without impact on chip area and power consumption 在不影响芯片面积和功耗的情况下提高时序误差容忍度

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523638

Ken Yano, Takanori Hayashida, Toshinori Sato

引用次数: 3

Runtime 3-D stacked cache management for chip-multiprocessors 芯片多处理器的运行时3-D堆叠缓存管理

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523592

Jongpil Jung, K. Kang, G. Micheli, C. Kyung

引用次数: 1

Reliability-constrained die stacking order in 3DICs under manufacturing variability 制造可变性下的三维集成电路可靠性约束的模具堆叠顺序

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523584

T. Chan, A. Kahng, Jiajia Li

{"title":"Reliability-constrained die stacking order in 3DICs under manufacturing variability","authors":"T. Chan, A. Kahng, Jiajia Li","doi":"10.1109/ISQED.2013.6523584","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523584","url":null,"abstract":"3D integrated circuits (3DICs) with through-silicon vias (TSVs) are an important direction for semiconductor-based products and “More than Moore” scaling. However, 3DICs bring simultaneous challenges of reliability (power and temperature in stacks of thinned die) as well as variability (performance and power) in advanced technology nodes. In this paper, we study variability-reliability interactions and optimizations in 3DICs. Initial motivating studies show that in the presence of manufacturing variability, different die stacking orders can lead to as much as 2 years (~44%) difference in MTTF of a 3DIC stack. We study MTTF-driven die-stacking optimization with consideration of variability, and propose a “rule-of-thumb” guideline for stacking optimization to improve peak temperature as well as reliability in 3DICs. We also propose integer-linear programming (ILP) methods for reliability-driven die-stacking optimization. Our methods can achieve ~7% and ~28% improvement in average and minimum MTTF, respectively, of 3DICs; we also achieve ~3% improvement in performance under fixed reliability constraints. Our stacking optimizations can help improve 3DIC product yields under reliability requirements. Our research also yields the notable observation that a limited amount of manufacturing variation can “help” improve 3DIC product reliability when die-stacking optimization is applied.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122186548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A novel 6T SRAM cell with asymmetrically gate underlap engineered FinFETs for enhanced read data stability and write ability 一种新型的6T SRAM单元，具有非对称栅极underlap设计的finfet，可增强读取数据的稳定性和写入能力

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523634

S. Salahuddin, Hailong Jiao, V. Kursun

引用次数: 48