International Symposium on Quality Electronic Design (ISQED)最新文献_第2页

Thermal-aware semi-dynamic power management for multicore systems with energy harvesting 具有能量收集的多核系统的热感知半动态电源管理

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523675

Yi Xiang, S. Pasricha

{"title":"Thermal-aware semi-dynamic power management for multicore systems with energy harvesting","authors":"Yi Xiang, S. Pasricha","doi":"10.1109/ISQED.2013.6523675","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523675","url":null,"abstract":"In this paper, we focus on power and thermal management for multicore embedded systems with solar energy harvesting as the power source and a periodic hard real-time task set as the workload. We design a novel semi-dynamic scheme, which reschedules tasks at the beginning of specified time epochs. By rejecting job instances of certain tasks until the next rescheduling point, our scheduler dispatches a subset of tasks that comply with the predicted energy budget and thermal conditions. Our approach reacts to run-time energy harvesting power variation without losing the consistency of the periodic task set, which helps to scale processor speed evenly by utilizing slack time efficiently without the need for complex slack reclamation algorithms, as in prior work. When applied to a multicore platform, our approach offers a chance to shut down cores and reassign tasks for superior energy efficiency. As a result, experimental results show up to 70% miss rate reduction compared to prior work. Unlike any prior work, our approach also integrates thermal management to reduce peak temperature while minimizing miss rate for energy harvesting embedded systems.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129377917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Impact of conventional and emerging interconnects on the circuit performance of various post-CMOS devices 传统互连和新兴互连对各种后cmos器件电路性能的影响

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523611

A. Ceyhan, A. Naeemi

引用次数: 11

System-level optimization and benchmarking for InAs nanowire based gate-all-around tunneling FETs 基于InAs纳米线的栅极全隧穿场效应管的系统级优化与基准测试

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523610

C. Pan, A. Ceyhan, A. Naeemi

引用次数: 3

A co-synthesis methodology for power delivery and data interconnection networks in 3D ICs 三维集成电路中电力传输和数据互连网络的协同综合方法

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523593

N. Kapadia, S. Pasricha

{"title":"A co-synthesis methodology for power delivery and data interconnection networks in 3D ICs","authors":"N. Kapadia, S. Pasricha","doi":"10.1109/ISQED.2013.6523593","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523593","url":null,"abstract":"A stable voltage supply is critical for multiprocessor system-on-chips (MPSoCs) to operate at near-optimal performance levels. The problem of IR drops in a Power Delivery Network (PDN) is very severe in 3D MPSoCs with network-on-chip (NoC) fabrics where the current in the PDN increases proportionally with the number of device layers. At the same time, with the increasing core counts in today's power-hungry MPSoCs, the already hard problem of voltage island-aware Network-on-Chip (NoC) design has become even more challenging. Even though the PDN and NoC design goals are non-overlapping, both the optimizations are interdependent. Unfortunately, designers today seldom consider design of the PDN while synthesizing NoCs. In this work, for the first time, we propose a novel system-level co-synthesis methodology that minimizes 3D NoC energy while meeting performance goals; and simultaneously optimizes the 3D PDN design while satisfying IR-drop constraints. Our experimental results show that the proposed co-synthesis methodology meets IR-drop constraints while minimizing energy consumption for several real-world applications, improving upon results from traditional system-level methodologies that perform PDN design and NoC synthesis separately.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126321375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

A versatile rail to rail current mode instrumentation amplifier with an embedded band-pass filter for bio-potential signal conditioning 一种多用途轨对轨电流模式仪表放大器，带有嵌入式带通滤波器，用于生物电位信号调理

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523685

A. Anvesha, M. Baghini

引用次数: 2

Resource allocation and consolidation in a multi-core server cluster using a Markov decision process model 使用马尔可夫决策过程模型的多核服务器集群中的资源分配和整合

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523677

Yanzhi Wang, Shuang Chen, H. Goudarzi, Massoud Pedram

{"title":"Resource allocation and consolidation in a multi-core server cluster using a Markov decision process model","authors":"Yanzhi Wang, Shuang Chen, H. Goudarzi, Massoud Pedram","doi":"10.1109/ISQED.2013.6523677","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523677","url":null,"abstract":"Distributed computing systems have attracted a lot of attention due to increasing demand for high performance computing and storage. Resource allocation is one of the most important challenges in the distributed systems especially when the clients have some Service Level Agreements (SLAs) and the total profit depends on how the system can meet these SLAs. In this paper, an SLA-based resource allocation problem in a server cluster is considered. The objective is to maximize the total profit, which is the total price gained from serving the clients subtracted by the operation cost of the server cluster. The total price depends on the average request response time for each client as defined in their utility functions, while the operating cost is related to the total energy consumption. A joint optimization framework is proposed, comprised of request dispatching, dynamic voltage and frequency scaling (DVFS) for individual cores, as well as server-level and core-level consolidations. Each core in the cluster is modeled using a continuous-time Markov decision process (CTMDP). A near-optimal hierarchical solution is proposed, consisting of a central manager and distributed local agents. Each local agent employs linear programming-based CTMDP solving method to solve the DVFS problem for the corresponding core. The central manager solves the request dispatching problem and finds the optimal number of turned on cores and servers for request processing, thereby achieving a desirable tradeoff between service request response time and power consumption. Experimental results demonstrate that the proposed near-optimal resource allocation and consolidation algorithm consistently outperforms baseline algorithms.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134261586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 29

Suspicious timing error prediction with in-cycle clock gating 周期内时钟门控的可疑定时误差预测

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523631

Youhua Shi, Hiroaki Igarashi, N. Togawa, M. Yanagisawa

引用次数: 15

Analysis and reliability test to improve the data retention performance of EPROM circuits 提高EPROM电路数据保留性能的分析与可靠性试验

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523622

Jiyuan Luan, M. Divita

{"title":"Analysis and reliability test to improve the data retention performance of EPROM circuits","authors":"Jiyuan Luan, M. Divita","doi":"10.1109/ISQED.2013.6523622","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523622","url":null,"abstract":"Data retention lifetime is an important specification for the long term durability of EPROM circuits. While most of the published EPROM data retention results are based on empirical data, this paper presents an analytical approach which can be used to quantify EPROM data retention lifetime based on the circuit implementation. Two types of EPROM circuits are analyzed- a single transistor EPROM cell as well as a differential EPROM circuit. Using this new approach, the EPROM data retention performance is converted to a minimal residual gate charge requirement of the EPROM device which can then be used to directly compare and analyze the data retention performance of the EPROM circuits. The results of the analysis and comparison suggest that circuit implementation has great impact on EPROM data retention lifetime, and they also provide valuable insights on ways to improve the reliability of EPROM circuits. The analysis result of this paper on the differential EPROM circuit is further validated by wafer level reliability test (WLR) completed on an actual IC implementation, which suggests a good agreement between theoretical analysis and actual WLR data.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114535625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Aging-aware timing analysis considering combined effects of NBTI and PBTI 考虑NBTI和PBTI联合作用的衰老感知时序分析

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523590

S. Kiamehr, F. Firouzi, M. Tahoori

引用次数: 29

A power-efficient on-chip linear regulator assisted by switched capacitors for fast transient regulation 一种低功耗的片上线性调节器，由开关电容辅助，用于快速瞬态调节

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523684

Suming Lai, Peng Li

引用次数: 1