International Symposium on Quality Electronic Design (ISQED)最新文献_第2页

Thermal-aware semi-dynamic power management for multicore systems with energy harvesting 具有能量收集的多核系统的热感知半动态电源管理

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523675

Yi Xiang, S. Pasricha

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引用次数: 5

Impact of conventional and emerging interconnects on the circuit performance of various post-CMOS devices 传统互连和新兴互连对各种后cmos器件电路性能的影响

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523611

A. Ceyhan, A. Naeemi

引用次数: 11

System-level optimization and benchmarking for InAs nanowire based gate-all-around tunneling FETs 基于InAs纳米线的栅极全隧穿场效应管的系统级优化与基准测试

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523610

C. Pan, A. Ceyhan, A. Naeemi

引用次数: 3

A co-synthesis methodology for power delivery and data interconnection networks in 3D ICs 三维集成电路中电力传输和数据互连网络的协同综合方法

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523593

N. Kapadia, S. Pasricha

{"title":"A co-synthesis methodology for power delivery and data interconnection networks in 3D ICs","authors":"N. Kapadia, S. Pasricha","doi":"10.1109/ISQED.2013.6523593","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523593","url":null,"abstract":"A stable voltage supply is critical for multiprocessor system-on-chips (MPSoCs) to operate at near-optimal performance levels. The problem of IR drops in a Power Delivery Network (PDN) is very severe in 3D MPSoCs with network-on-chip (NoC) fabrics where the current in the PDN increases proportionally with the number of device layers. At the same time, with the increasing core counts in today's power-hungry MPSoCs, the already hard problem of voltage island-aware Network-on-Chip (NoC) design has become even more challenging. Even though the PDN and NoC design goals are non-overlapping, both the optimizations are interdependent. Unfortunately, designers today seldom consider design of the PDN while synthesizing NoCs. In this work, for the first time, we propose a novel system-level co-synthesis methodology that minimizes 3D NoC energy while meeting performance goals; and simultaneously optimizes the 3D PDN design while satisfying IR-drop constraints. Our experimental results show that the proposed co-synthesis methodology meets IR-drop constraints while minimizing energy consumption for several real-world applications, improving upon results from traditional system-level methodologies that perform PDN design and NoC synthesis separately.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126321375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

A versatile rail to rail current mode instrumentation amplifier with an embedded band-pass filter for bio-potential signal conditioning 一种多用途轨对轨电流模式仪表放大器，带有嵌入式带通滤波器，用于生物电位信号调理

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523685

A. Anvesha, M. Baghini

引用次数: 2

Resource allocation and consolidation in a multi-core server cluster using a Markov decision process model 使用马尔可夫决策过程模型的多核服务器集群中的资源分配和整合

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523677

Yanzhi Wang, Shuang Chen, H. Goudarzi, Massoud Pedram

{"title":"Resource allocation and consolidation in a multi-core server cluster using a Markov decision process model","authors":"Yanzhi Wang, Shuang Chen, H. Goudarzi, Massoud Pedram","doi":"10.1109/ISQED.2013.6523677","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523677","url":null,"abstract":"Distributed computing systems have attracted a lot of attention due to increasing demand for high performance computing and storage. Resource allocation is one of the most important challenges in the distributed systems especially when the clients have some Service Level Agreements (SLAs) and the total profit depends on how the system can meet these SLAs. In this paper, an SLA-based resource allocation problem in a server cluster is considered. The objective is to maximize the total profit, which is the total price gained from serving the clients subtracted by the operation cost of the server cluster. The total price depends on the average request response time for each client as defined in their utility functions, while the operating cost is related to the total energy consumption. A joint optimization framework is proposed, comprised of request dispatching, dynamic voltage and frequency scaling (DVFS) for individual cores, as well as server-level and core-level consolidations. Each core in the cluster is modeled using a continuous-time Markov decision process (CTMDP). A near-optimal hierarchical solution is proposed, consisting of a central manager and distributed local agents. Each local agent employs linear programming-based CTMDP solving method to solve the DVFS problem for the corresponding core. The central manager solves the request dispatching problem and finds the optimal number of turned on cores and servers for request processing, thereby achieving a desirable tradeoff between service request response time and power consumption. Experimental results demonstrate that the proposed near-optimal resource allocation and consolidation algorithm consistently outperforms baseline algorithms.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134261586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 29

Reliability-constrained die stacking order in 3DICs under manufacturing variability 制造可变性下的三维集成电路可靠性约束的模具堆叠顺序

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523584

T. Chan, A. Kahng, Jiajia Li

{"title":"Reliability-constrained die stacking order in 3DICs under manufacturing variability","authors":"T. Chan, A. Kahng, Jiajia Li","doi":"10.1109/ISQED.2013.6523584","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523584","url":null,"abstract":"3D integrated circuits (3DICs) with through-silicon vias (TSVs) are an important direction for semiconductor-based products and “More than Moore” scaling. However, 3DICs bring simultaneous challenges of reliability (power and temperature in stacks of thinned die) as well as variability (performance and power) in advanced technology nodes. In this paper, we study variability-reliability interactions and optimizations in 3DICs. Initial motivating studies show that in the presence of manufacturing variability, different die stacking orders can lead to as much as 2 years (~44%) difference in MTTF of a 3DIC stack. We study MTTF-driven die-stacking optimization with consideration of variability, and propose a “rule-of-thumb” guideline for stacking optimization to improve peak temperature as well as reliability in 3DICs. We also propose integer-linear programming (ILP) methods for reliability-driven die-stacking optimization. Our methods can achieve ~7% and ~28% improvement in average and minimum MTTF, respectively, of 3DICs; we also achieve ~3% improvement in performance under fixed reliability constraints. Our stacking optimizations can help improve 3DIC product yields under reliability requirements. Our research also yields the notable observation that a limited amount of manufacturing variation can “help” improve 3DIC product reliability when die-stacking optimization is applied.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122186548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A novel 6T SRAM cell with asymmetrically gate underlap engineered FinFETs for enhanced read data stability and write ability 一种新型的6T SRAM单元，具有非对称栅极underlap设计的finfet，可增强读取数据的稳定性和写入能力

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523634

S. Salahuddin, Hailong Jiao, V. Kursun

引用次数: 48

Performance and cache access time of SRAM-eDRAM hybrid caches considering wire delay 考虑线延迟的SRAM-eDRAM混合缓存的性能和缓存访问时间

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523661

Young-Ho Gong, H. Jang, S. Chung

引用次数: 3

Runtime 3-D stacked cache management for chip-multiprocessors 芯片多处理器的运行时3-D堆叠缓存管理

International Symposium on Quality Electronic Design (ISQED) Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523592

Jongpil Jung, K. Kang, G. Micheli, C. Kyung

引用次数: 1