Impact of conventional and emerging interconnects on the circuit performance of various post-CMOS devices

A. Ceyhan, A. Naeemi
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引用次数: 11

Abstract

The trade-offs between the technology parameters of various interconnect technologies are investigated on the basis of their impacts on the circuit performances of emerging post-CMOS devices. In this paper, carbon nanotube field-effect transistor (CNFET), nanowire-based gate-all-around (GAA) tunneling field-effect transistor (TFET), FinFET and sub-threshold CMOS circuits are studied. Each of these devices are paired with the conventional Cu/low-k interconnect, single-wall carbon nanotube (SWNT) interconnect manufactured in horizontal bundles or in a single layer, and multi-layer graphene nanoribbon (GNR) interconnect. The relative performances of all these interconnect technologies with each type of device are evaluated. The interconnect technology option that gives the best performance in terms of circuit delay, energy-per-bit and energy-delay product (EDP) is reported for each of the device technologies.
传统互连和新兴互连对各种后cmos器件电路性能的影响
基于对新兴后cmos器件电路性能的影响,研究了各种互连技术参数之间的权衡。本文研究了碳纳米管场效应晶体管(CNFET)、基于纳米线的栅极全能(GAA)隧道场效应晶体管(TFET)、FinFET和亚阈值CMOS电路。每种器件都与传统的Cu/低k互连、水平束或单层制造的单壁碳纳米管(SWNT)互连和多层石墨烯纳米带(GNR)互连配对。评估了所有这些互连技术与每种类型器件的相对性能。对于每种器件技术,报告了在电路延迟、每比特能量和能量延迟产品(EDP)方面提供最佳性能的互连技术选项。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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