Reliability-aware and energy-efficient synthesis of NoC based MPSoCs

Yong Zou, S. Pasricha
{"title":"Reliability-aware and energy-efficient synthesis of NoC based MPSoCs","authors":"Yong Zou, S. Pasricha","doi":"10.1109/ISQED.2013.6523678","DOIUrl":null,"url":null,"abstract":"In sub-65nm CMOS process technologies, networks-on-chip (NoC) are increasingly susceptible to transient faults (i.e., soft errors). To achieve fault tolerance, Triple Modular Redundancy (TMR) and Hamming Error Correction Codes (HECC) are often employed by designers to protect buffers used in NoC components. However, these mechanisms to achieve fault resilience introduce power dissipation overheads that can disrupt stringent chip power budgets and thermal constraints. In this paper, we propose a novel design-time framework (RESYN) to trade-off energy consumption and reliability in the NoC fabric at the system level for MPSoCs. RESYN employs a nested evolutionary algorithm approach to guide the mapping of cores on a die, and opportunistically determine locations to insert fault tolerance mechanisms in the NoC to minimize energy while satisfying reliability constraints. Our experimental results show that RESYN can reduce energy costs by 14.5% on average compared to a fully protected NoC, while still maintaining more than a 90% fault tolerance. If higher levels of reliability are desired, RESYN can generate a Pareto set of solutions allowing designers to select the most energy-efficient solution for any reliability goal. Given the increasing importance of reliability in the nanometer era for MPSoCs, this work provides important perspectives that can guide the reduction of overheads of reliable NoC design.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Symposium on Quality Electronic Design (ISQED)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED.2013.6523678","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10

Abstract

In sub-65nm CMOS process technologies, networks-on-chip (NoC) are increasingly susceptible to transient faults (i.e., soft errors). To achieve fault tolerance, Triple Modular Redundancy (TMR) and Hamming Error Correction Codes (HECC) are often employed by designers to protect buffers used in NoC components. However, these mechanisms to achieve fault resilience introduce power dissipation overheads that can disrupt stringent chip power budgets and thermal constraints. In this paper, we propose a novel design-time framework (RESYN) to trade-off energy consumption and reliability in the NoC fabric at the system level for MPSoCs. RESYN employs a nested evolutionary algorithm approach to guide the mapping of cores on a die, and opportunistically determine locations to insert fault tolerance mechanisms in the NoC to minimize energy while satisfying reliability constraints. Our experimental results show that RESYN can reduce energy costs by 14.5% on average compared to a fully protected NoC, while still maintaining more than a 90% fault tolerance. If higher levels of reliability are desired, RESYN can generate a Pareto set of solutions allowing designers to select the most energy-efficient solution for any reliability goal. Given the increasing importance of reliability in the nanometer era for MPSoCs, this work provides important perspectives that can guide the reduction of overheads of reliable NoC design.
基于NoC的mpsoc的可靠性感知和节能合成
在65nm以下的CMOS工艺技术中,片上网络(NoC)越来越容易受到瞬态故障(即软错误)的影响。为了实现容错,设计人员经常使用三模冗余(TMR)和汉明纠错码(HECC)来保护NoC组件中使用的缓冲区。然而,这些实现故障恢复的机制引入了功耗开销,可能会破坏严格的芯片功率预算和热约束。在本文中,我们提出了一种新的设计时框架(RESYN)来权衡mpsoc系统级NoC结构中的能耗和可靠性。RESYN采用嵌套进化算法方法来指导内核在芯片上的映射,并根据需要确定在NoC中插入容错机制的位置,以在满足可靠性约束的同时最小化能量。我们的实验结果表明,与完全保护的NoC相比,RESYN可以平均降低14.5%的能源成本,同时仍然保持90%以上的容错性。如果需要更高级别的可靠性,RESYN可以生成一个帕累托解决方案集,允许设计人员为任何可靠性目标选择最节能的解决方案。考虑到纳米时代mpsoc可靠性的重要性日益增加,这项工作提供了重要的视角,可以指导降低可靠NoC设计的开销。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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