2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)最新文献_第6页

A Self-coupled DT MASH ΔΣ Modulator with High Tolerance to Noise Leakage 一种高耐噪声泄漏的自耦合DT MASH ΔΣ调制器

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2020-12-08 DOI: 10.1109/APCCAS50809.2020.9301686

Gaofeng Tan, Haolin Lu, Xinyu Qin, Jiliang Zhang, Jingying Zhang, Y. Liu, Liang Qi

引用次数: 0

Digital Phase Estimation through an I/Q Approach for Angle of Arrival Full-Hardware Localization 基于I/Q方法的到达角全硬件定位数字相位估计

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2020-12-08 DOI: 10.1109/APCCAS50809.2020.9301691

A. Florio, G. Avitabile, G. Coviello

引用次数: 5

A RISC-V SoC for Mobile Payment Based on Visible Light Communication 一种基于可见光通信的RISC-V移动支付SoC

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2020-12-08 DOI: 10.1109/APCCAS50809.2020.9301688

Xinchao Zhong, Chiu-Wing Sham, Longyu Ma

引用次数: 6

Missing Temperature Data Recovery Methods Based on Smoothness, Bandlimitedness and Sparseness Priors 基于平滑、带宽限制和稀疏先验的缺失温度数据恢复方法

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2020-12-08 DOI: 10.1109/APCCAS50809.2020.9301671

C. Tseng, Su-Ling Lee

引用次数: 1

An Area-Power-Efficient AFE with NS-SAR ADC For High-Frequency Ultrasound Applications 用于高频超声应用的具有NS-SAR ADC的区域节能AFE

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2020-12-08 DOI: 10.1109/APCCAS50809.2020.9301650

Yimin Wu, Shuai Li, L. Luo, Fan Ye, Junyan Ren

引用次数: 1

Performance Analysis of Non-Profiled Side Channel Attacks Based on Convolutional Neural Networks 基于卷积神经网络的非侧信道攻击性能分析

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2020-12-08 DOI: 10.1109/APCCAS50809.2020.9301673

Ngoc-Tuan Do, Van‐Phuc Hoang, Van-Sang Doan

{"title":"Performance Analysis of Non-Profiled Side Channel Attacks Based on Convolutional Neural Networks","authors":"Ngoc-Tuan Do, Van‐Phuc Hoang, Van-Sang Doan","doi":"10.1109/APCCAS50809.2020.9301673","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301673","url":null,"abstract":"There are emerging issues about side channel at-tacks (SCAs) on the cryptographic devices which are widely used today for securing secret information. Recently, the neural networks have been introduced as a new promising approach to perform SCA for hardware security evaluation of cryptographic algorithms. In this work, we present a non-profiled SCA using convolutional neural networks (CNNs) on an 8-bit AVR micro-controller device running the AES-128 cryptographic algorithm. We aim to point out the practical issues that occurs in CNN based SCA methods using the aligned power traces with a large number of samples. Furthermore, a method to build a suitable dataset for CNN training is introduced. Especially, practical experiment results of the CNN based SCA methods and a comprehensive investigation on the effect of noise are also presented. These experiments are performed with the original power traces and additive Gaussian noise. The results show that the CNN based SCA with our constructed dataset provides reliable results for non-profiled attacks. However, it is also shown that the Gaussian noise added on power traces becomes a serious problem.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115056320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Efficient FPGA design for Convolutions in CNN based on FFT-pruning 基于fft剪枝的CNN卷积高效FPGA设计

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2020-12-08 DOI: 10.1109/APCCAS50809.2020.9301653

Liulu He, Xiaoru Xie, Jun Lin, Zhongfeng Wang

{"title":"Efficient FPGA design for Convolutions in CNN based on FFT-pruning","authors":"Liulu He, Xiaoru Xie, Jun Lin, Zhongfeng Wang","doi":"10.1109/APCCAS50809.2020.9301653","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301653","url":null,"abstract":"Fast algorithms of convolution, such as Winograd and fast Fourier transformation (FFT), have been widely used in many FPGA-based CNN accelerators to reducing the complexity of multiplication. The core idea for those fast algorithms is reducing the number of multiplication at the cost of more additions. However, increased additions take up a significant portion in the whole LUT resources in many cases, which forms a new bottleneck in the corresponding hardware design. In this paper, we theoretically analyze the relationship between the reduced multiplications and the increased additions, and propose an reduced complexity fast FFT convolution algorithm by intelligently employing the FFT-pruning method to remove redundant additions. Compared with the state-of-the-art algorithm, our algorithm can reduce more than 50% of additions. Moreover, the proposed algorithm has better numerical accuracy and comparable multiplication complexity compared to the most efficient Winograd algorithm. Additionally, an efficient reconfigurable architecture of the proposed algorithm is also developed to accelerate convolutional layers with various kernel sizes. Implemented with Xilinx ZC706, the proposed architecture achieves 200.6 GOPS on convolutional layers of ResNet-50 with 61% higher resources efficiency with respect to LUT consumption compared to prior arts.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126141030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Dilated Residual Convolutional Neural Networks for Low-Dose CT Image Denoising 基于扩展残差卷积神经网络的低剂量CT图像去噪

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2020-12-08 DOI: 10.1109/APCCAS50809.2020.9301693

Nguyen Thanh Trung, D. Trinh, N. Trung, T. T. T. Quynh, M. Luu

引用次数: 7

Using Fully Connected and Convolutional Net for GAN-Based Face Swapping 基于全连接卷积网络的gan人脸交换

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2020-12-08 DOI: 10.1109/APCCAS50809.2020.9301665

Bo-Shue Lin, Ding-Wen Hsu, Chin-Han Shen, Hsu-Feng Hsiao

引用次数: 2

MESSAGE FROM TPC CO-CHAIR 来自TPC联合主席的信息

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2020-12-08 DOI: 10.1109/apccas50809.2020.9301649

Lan-Da Van, K. Dang, I. Verbauwhede, Van‐Phuc Hoang

引用次数: 0