2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)最新文献_第5页

High Efficiency Early-Complete Brute Force Elimination Method for Security Analysis of Camouflage IC 伪装集成电路安全性分析的高效早完全蛮力消除方法

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2020-12-08 DOI: 10.1109/APCCAS50809.2020.9301666

Weng-Geng Ho, Chuan-Seng Ng, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, B. Gwee

{"title":"High Efficiency Early-Complete Brute Force Elimination Method for Security Analysis of Camouflage IC","authors":"Weng-Geng Ho, Chuan-Seng Ng, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, B. Gwee","doi":"10.1109/APCCAS50809.2020.9301666","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301666","url":null,"abstract":"We propose a high efficiency Early-Complete Brute Force Elimination method that speeds up the analysis flow of the Camouflage Integrated Circuit (IC). The proposed method is targeted for security qualification of the Camouflaged IC netlists in Intellectual Property (IP) protection. There are two main features in the proposed method. First, the proposed method features immediate elimination of the incorrect Camouflage gates combination for the rest of computation, concentrating the resources into other potential correct Camouflage gates combination. Second, the proposed method features early complete, i.e. revealing the correct Camouflage gates once all incorrect gates combination are eliminated, increasing the computation speed for the overall security analysis. Based on the Python programming platform, we implement the algorithm of the proposed method and test it for three circuits including ISCAS’89 benchmarks. From the simulation results, our proposed method, on average, features 71% lesser number of trials and 79% shorter run time as compared to the conventional method in revealing the correct Camouflage gates from the Camouflaged IC netlist.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116377290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2020-12-08 DOI: 10.1109/apccas50809.2020.9301648

引用次数: 0

A Spur-Free Low-Complexity Hybrid Nested Bus-Splitting/SP-MASH Digital Delta-Sigma Modulator 无杂散低复杂度混合嵌套总线分割/SP-MASH数字Delta-Sigma调制器

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2020-12-08 DOI: 10.1109/APCCAS50809.2020.9301657

Tieu-Khanh Luong, Hong-Hanh Hoang, Hoang-Anh Nguyen-Minh, C. D. Bui, Son Bui, Trung‐Kien Nguyen

{"title":"A Spur-Free Low-Complexity Hybrid Nested Bus-Splitting/SP-MASH Digital Delta-Sigma Modulator","authors":"Tieu-Khanh Luong, Hong-Hanh Hoang, Hoang-Anh Nguyen-Minh, C. D. Bui, Son Bui, Trung‐Kien Nguyen","doi":"10.1109/APCCAS50809.2020.9301657","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301657","url":null,"abstract":"Digital Delta-Sigma Modulators (DDSMs) are widely used in integrated circuits for wireless communications, particularly in fractional-N frequency synthesizers and oversampled digital-to-analog converters (DACs). A large bus-width is often required to have fine frequency resolution especially in 5G, which causes a high hardware complexity. A nested bus-splitting DDSM has advantages of potential speed and compact area over the conventional DDSMs, and hence reduces hardware complexity thanks to its smaller bus width. However, this architecture still suffers from spurious tones, especially in the case of constant or periodic inputs. In this work, an SP-MASH architecture has been embedded into a nested bus-splitting DDSM to overcome the spur problem. The synthesis result by Synopsys Design Compiler using TSMC 28 nm CMOS standard cell shows that the advantage of hardware cost was preserved while the spur-free performance was achieved by this hybrid scheme. Its function and effectiveness was also successfully verified with Xilinx Virtex UltraScale+ field-programmable-gate-array (FPGA).","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122871904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

APCCAS 2020 Contributor Page APCCAS 2020贡献者页面

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2020-12-08 DOI: 10.1109/apccas50809.2020.9301656

引用次数: 0

Axial Resolution Enhacement of Light-Sheet Microscopy via two Light-Sheets 通过两个光片增强光片显微镜的轴向分辨率

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2020-12-08 DOI: 10.1109/APCCAS50809.2020.9301664

Vannhu Le, MinhNghia Pham, Vandang Hoang

引用次数: 1

Graph Saliency Network: Using Graph Convolution Network on Saliency Detection 图显著性网络:利用图卷积网络进行显著性检测

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2020-12-08 DOI: 10.1109/APCCAS50809.2020.9301708

Heng-Sheng Lin, Jian-Jiun Ding, Jin-Yu Huang

{"title":"Graph Saliency Network: Using Graph Convolution Network on Saliency Detection","authors":"Heng-Sheng Lin, Jian-Jiun Ding, Jin-Yu Huang","doi":"10.1109/APCCAS50809.2020.9301708","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301708","url":null,"abstract":"Saliency detection is to detect the unique region of an image that may attract human attention. It is widely used in image/video segmentation, image enhancement, and image compression. Conventionally, saliency detection problem was solved by graph-based method cooperate with low-level features and heuristic rules. Recently, the convolutional neural networks (CNNs) based methods have been thrived in computer vision area and graph convolutional networks (GCNs), which are extended from the CNN, have been used in many graph data representations and also shown promising result in node classification problem. We proposed a novel saliency detection neural network model called the Graph Saliency Network (GSN), which use the Graph Convolutional Network as main architecture and the Jumping Knowledge Network as our backbone. For the graph creation, the Region Adjacency Graph is adopted as the image-graph transformation in the proposed architecture to propagate information through edges from the spatial boundary. We also revisit several graph-based saliency detection methods for our node feature representation. The propagation model of the GSN maintain the spatial relation of the CNN with a more flexible way and has less parameters to be optimized than the CNN from the advantage of information compression in superpixel and graph. Simulations showed that, using the proposed GCN- based model together with low-level features and heuristic rules, a saliency detection result with very less mean absolute error (MAE) can be achieved.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125834801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Frequency-Tunable Quasi-Elliptic Filter Using Liquid Metal 液态金属准椭圆滤波器的频率可调

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2020-12-08 DOI: 10.1109/APCCAS50809.2020.9301676

Matthew Brown, C. Saavedra

引用次数: 3

High-Performance Implementation of Adaptive IQ Mismatch Compensator in Direct-Conversion Transceiver 直接转换收发器中自适应IQ失配补偿器的高性能实现

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2020-12-08 DOI: 10.1109/APCCAS50809.2020.9301681

Van-Toan Nguyen, Viet-Son Bui, Trung‐Kien Nguyen

引用次数: 1

ReRAM Device and Circuit Co-Design Challenges in Nano-scale CMOS Technology 纳米级CMOS技术中的ReRAM器件和电路协同设计挑战

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2020-12-08 DOI: 10.1109/APCCAS50809.2020.9301707

Lu Lu, Ju Eon Kim, Vishal Sharma, T. T. Kim

引用次数: 3

ECC processor over the Koblitz curves with τ-NAF Converter and Square-Square-Add Algorithm 用τ-NAF变换器和Square-Square-Add算法实现Koblitz曲线上的ECC处理器

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2020-12-08 DOI: 10.1109/APCCAS50809.2020.9301654

Ting-Yuan Wang, Tsung-Te Liu

引用次数: 0