伪装集成电路安全性分析的高效早完全蛮力消除方法

Weng-Geng Ho, Chuan-Seng Ng, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, B. Gwee
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引用次数: 0

摘要

提出了一种高效的早期完全蛮力消除方法,加快了伪装集成电路(IC)的分析流程。本文提出的方法是针对伪装集成电路网络在知识产权保护中的安全鉴定问题。该方法有两个主要特点。首先,该方法的特点是在剩余的计算中立即消除不正确的伪装门组合,将资源集中到其他可能正确的伪装门组合上。其次,该方法具有早完备的特点,即在排除所有不正确的伪装门组合后显示正确的伪装门,提高了整体安全性分析的计算速度。基于Python编程平台,我们实现了该方法的算法,并在ISCAS ' 89基准测试等三个电路上进行了测试。从仿真结果来看,与传统方法相比,我们提出的方法在从伪装IC网表中显示正确的伪装门时,平均减少了71%的试验次数和79%的运行时间。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
High Efficiency Early-Complete Brute Force Elimination Method for Security Analysis of Camouflage IC
We propose a high efficiency Early-Complete Brute Force Elimination method that speeds up the analysis flow of the Camouflage Integrated Circuit (IC). The proposed method is targeted for security qualification of the Camouflaged IC netlists in Intellectual Property (IP) protection. There are two main features in the proposed method. First, the proposed method features immediate elimination of the incorrect Camouflage gates combination for the rest of computation, concentrating the resources into other potential correct Camouflage gates combination. Second, the proposed method features early complete, i.e. revealing the correct Camouflage gates once all incorrect gates combination are eliminated, increasing the computation speed for the overall security analysis. Based on the Python programming platform, we implement the algorithm of the proposed method and test it for three circuits including ISCAS’89 benchmarks. From the simulation results, our proposed method, on average, features 71% lesser number of trials and 79% shorter run time as compared to the conventional method in revealing the correct Camouflage gates from the Camouflaged IC netlist.
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