2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)最新文献_第7页

A Single-Stage Delay-Tuned Active Rectifier for Constant-Current Constant-Voltage Wireless Charging 用于恒流恒压无线充电的单级延迟调谐有源整流器

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2020-12-08 DOI: 10.1109/APCCAS50809.2020.9301663

Xianglong Bai, Fangyu Mao, Yan Lu, Chenchang Zhan, R. Martins

{"title":"A Single-Stage Delay-Tuned Active Rectifier for Constant-Current Constant-Voltage Wireless Charging","authors":"Xianglong Bai, Fangyu Mao, Yan Lu, Chenchang Zhan, R. Martins","doi":"10.1109/APCCAS50809.2020.9301663","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301663","url":null,"abstract":"This paper presents a single-stage regulated active rectifier with two operation modes of constant-current charging mode (CC) and constant-voltage charging mode (CV) for battery wireless charging. With the delay-tuned active rectifier, the proposed wireless charger can realize AC-DC power rectification, voltage regulation, CC and CV battery charging in a single power stage with high efficiency and small volume. The adaptive tuning of the delay of the power NMOS gate-drive signals, regulates the average charging current at a constant value for the CC mode, and the output voltage for the CV mode. The circuit achieves a precise average AC current sensing with a replica sensing stage. The utilization of a hysteresis comparator detects the output voltage and changes the charging mode during the battery charging process. The proposed single-stage wireless charger, designed in standard 0.35μm CMOS, operates at 6.78MHz. Simulation results show that the efficiency of the entire CC mode is higher than 89.8% with the battery voltage ranging from 2.8V to 4.2V. And we obtain a peak efficiency of 94.3% with 4.2 V and 1A output.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"221 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132522778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A lightweight Max-Pooling method and architecture for Deep Spiking Convolutional Neural Networks 一种轻量级的深度尖峰卷积神经网络的最大池化方法和体系结构

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2020-12-08 DOI: 10.1109/APCCAS50809.2020.9301703

Duy-Anh Nguyen, Xuan-Tu Tran, K. Dang, F. Iacopi

{"title":"A lightweight Max-Pooling method and architecture for Deep Spiking Convolutional Neural Networks","authors":"Duy-Anh Nguyen, Xuan-Tu Tran, K. Dang, F. Iacopi","doi":"10.1109/APCCAS50809.2020.9301703","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301703","url":null,"abstract":"The training of Deep Spiking Neural Networks (DSNNs) is facing many challenges due to the non-differentiable nature of spikes. The conversion of a traditional Deep Neural Networks (DNNs) to its DSNNs counterpart is currently one of the prominent solutions, as it leverages many state-of-the-art pre-trained models and training techniques. However, the conversion of max-pooling layer is a non-trivia task. The state-of-the-art conversion methods either replace the max-pooling layer with other pooling mechanisms or use a max-pooling method based on the cumulative number of output spikes. This incurs both memory storage overhead and increases computational complexity, as one inference in DSNNs requires many timesteps, and the number of output spikes after each layer needs to be accumulated. In this paper1, we propose a novel max-pooling mechanism that is not based on the number of output spikes but is based on the membrane potential of the spiking neurons. Simulation results show that our approach still preserves classification accuracies on MNIST and CIFARIO dataset. Hardware implementation results show that our proposed hardware block is lightweight with an area cost of 15.3kGEs, at a maximum frequency of 300 MHz.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130801154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Random Number Generator Based on Skew-tent Map and Chaotic Sampling 基于斜帐篷映射和混沌采样的随机数发生器

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2020-12-08 DOI: 10.1109/APCCAS50809.2020.9301661

Salih Ergün, Sercan Tanriseven

引用次数: 2

Hardware Attack and Assurance with Machine Learning: A Security Threat to Circuits and Systems 机器学习的硬件攻击和保证:对电路和系统的安全威胁

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2020-12-08 DOI: 10.1109/APCCAS50809.2020.9301658

B. Gwee

{"title":"Hardware Attack and Assurance with Machine Learning: A Security Threat to Circuits and Systems","authors":"B. Gwee","doi":"10.1109/APCCAS50809.2020.9301658","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301658","url":null,"abstract":"Summary form only given, as follows. The complete presentation was not made available for publication as part of the conference proceedings. Banking, defence applications and cryptosystems often demand security features, including cryptography, tamper resistance, stealth, and etc., by means of hardware approaches and/or software approaches to prevent data leakages. The hardware physical attacks or commonly known as side channel attacks have been employed to extract the secret keys of the encrypted algorithms implemented in hardware devices by analyzing their physical parameters such as power dissipation, electromagnetic interference and timing information. Altered functions or unauthorized modules may be added to the circuit design during the shipping and manufacturing process, bringing in security threats to the deployed systems. In this presentation, we will discuss hardware assurance from both device level and circuit level, and present how machine learning techniques can be utilized. At the device level, we will first provide an overview of the different cryptography algorithms and present the side channel attacks, particularly the powerful Correlation Power Analysis (CPA) and Correlation Electromagnetic Analysis (CEMA) with a leakage model that can be used to reveal the secret keys of the cryptosystems. We will then discuss several countermeasure techniques and present how highly secured microchips can be designed based on these techniques. At the circuit level, we will provide an overview of manufactured IC circuit analysis through invasive IC delayering and imaging. We then present several machine learning techniques that can be efficiently applied to the retrieval of circuit contact points and connections for further netlist/functional analysis.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133884281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of SRAM cell using Voltage Lowering and Stacking Techniques for Low Power Applications 基于低功耗降压和堆叠技术的SRAM单元设计

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2020-12-08 DOI: 10.1109/APCCAS50809.2020.9301672

J. Mishra, P. K. Misra, M. Goswami

{"title":"Design of SRAM cell using Voltage Lowering and Stacking Techniques for Low Power Applications","authors":"J. Mishra, P. K. Misra, M. Goswami","doi":"10.1109/APCCAS50809.2020.9301672","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301672","url":null,"abstract":"The internet of things and intelligent wearable device are bringing new challenges to IC design, where the low static power dissipation and high stability is required for portable devices. In this paper, a design of static random access memory (SRAM) cell has been proposed with high stability and low static power dissipation. In this work a voltage lowering circuit has been used to enhance the write ability while read buffer has been used for enhance the read stability of SRAM cell. Moreover the stack transistor has also been used for reducing the leakage current which results in reduction of static power dissipation. This has been noticed that there is an enhancement in the WSNM of proposed design by 11%, 22%, 35%, 13.4% as compared to 6T [4], 7T [7], 8T [8], 10T [10] SRAM cells respectively, while reduction of 0.78% as compared to 9T [9]. It has also been observed that there is a reduction of 35%, 22%, 42.9%, 61% in the static power dissipation of proposed design as compared to 6T [4], 7T [7], 9T [9] and 10T [10] SRAM cells respectively. The proposed circuit is designed using 28 nm CMOS technology node at 1 V supply voltage while the cadence virtuoso tool has been used for verification of proposed design.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"11 suppl_1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115607590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

"Truth from Practice, Learning beyond Teaching" Exploration in Teaching Analog Integrated Circuit “实践出真知，学于教”模拟集成电路教学探索

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2020-12-08 DOI: 10.1109/APCCAS50809.2020.9301669

Hua Fan, Xiaohu Qi, Q. Feng

{"title":"\"Truth from Practice, Learning beyond Teaching\" Exploration in Teaching Analog Integrated Circuit","authors":"Hua Fan, Xiaohu Qi, Q. Feng","doi":"10.1109/APCCAS50809.2020.9301669","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301669","url":null,"abstract":"This paper presents \"Truth from Practice, Learning beyond Teaching\", a new teaching model of engineering circuit courses. It is proposed to use experimental learning to drive theoretical study, which make students better fit the company’s work, transform the traditional test score based final examination to the process evaluation, which is consistent with the proposed teaching model. This paper presents a curriculum framework that establishes the combination of higher education and social production used in the supply power circuit course. The syllabus of the reform includes lectures, laboratories, projects and the procedure for evaluation focuses on process. In the contest of higher engineering education, autonomous learning and innovation are seen at the key factors of knowledge-based society, adapt the proposed education approach to cope with ongoing and future problems. The use of this teaching model to significantly motivates students to broaden their knowledge widely and to improve the quality of the course, enable scientific research techniques to solve practical problems more effectively, and avoid the blindness of talent cultivation.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114484952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Capacitive recombination calibration method to improve the performance of SAR ADC 提高SAR ADC性能的电容复合校准方法

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2020-12-08 DOI: 10.1109/APCCAS50809.2020.9301689

Hua Fan, Xinjie Wu, Q. Feng, Kelin Zhang, Jia Zhang

引用次数: 0

Damage-Position Identification of Wooden-House Models for Structural Health Monitoring Using Machine Learning 基于机器学习的结构健康监测木结构模型损伤位置识别

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2020-12-08 DOI: 10.1109/APCCAS50809.2020.9301694

Kohei Koike, Kenta Suzuki, Mengnan Ke, K. Mori, Takumi Ito, Takayuki Kawahara

{"title":"Damage-Position Identification of Wooden-House Models for Structural Health Monitoring Using Machine Learning","authors":"Kohei Koike, Kenta Suzuki, Mengnan Ke, K. Mori, Takumi Ito, Takayuki Kawahara","doi":"10.1109/APCCAS50809.2020.9301694","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301694","url":null,"abstract":"We used our previously proposed structural-health-monitoring system that uses machine learning and requires only one sensor to identify damage locations of braces and walls and applied it to two wooden-house model to identify damage locations. In our previous studies, we succeeded in identifying damage locations with 90% accuracy in a wooden-house model with two crossed braces by using our system. We also conducted an experiment on an actual wooden house in Oita prefecture, Japan and identified the damage locations with an accuracy of 86.0%. For this study, we used this system to identify the damage locations of a wooden-house model with only 28 diagonal braces and another wooden-house model with 26 walls. We removed only one brace and one wall from each model and assumed that they were the damage locations. Shaking was generated by attaching a motor as a vibration source to models. The vibration of models was detected using a piezoelectric sensor, and the output voltage waveform of the piezoelectric sensor was recorded using a digital oscilloscope. This output voltage waveform was analyzed using a neural network. Using a three-layer neural network, four sides of both models were identified separately and more than 95% of the braces and walls were recorded. Damage locations throughout the entire braced and walled models were then identified using a neural network with three to ten layers. As a result, the identification rate was 94.5% for the braced model with the neural network with four layers and 97.8% for the walled model with the neural network with five layers.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115794170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Fast Permutation Architecture on Encrypted Data for Secure Neural Network Inference 用于安全神经网络推理的加密数据快速置换体系结构

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2020-12-08 DOI: 10.1109/APCCAS50809.2020.9301698

Xiao Hu, Jing Tian, Zhongfeng Wang

{"title":"Fast Permutation Architecture on Encrypted Data for Secure Neural Network Inference","authors":"Xiao Hu, Jing Tian, Zhongfeng Wang","doi":"10.1109/APCCAS50809.2020.9301698","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301698","url":null,"abstract":"Recently, the secure neural network inference, an organic combination of the homomorphic encryption (HE) and the deep neural network (DNN), has attracted much attention. Nevertheless, the large number computations, brought by the HE scheme, form the bottleneck for real-time applications. A significant portion of the network is the permutation (Perm), which is mainly made up of the number theoretic transform (NTT). In this paper, for the first time, we propose an efficient architecture for the Perm by incorporating algorithmic transformations and architectural level optimizations. First, the core butterfly unit (BU) of NTT is optimized, which reduces the multiplication operations by about 30% compared with the original BU. Then, based on the optimization, a highly parallelized architecture is devised for the Perm. The operations in different modules are well managed by a merging strategy to balance the data path and reduce the memory access. The proposed architecture is synthesized under the TSMC 28-nm CMOS technology. The experimental results show that for the ciphertext size of 2048×60 bits, the proposed design achieves a 7.54x speedup compared to the implementation on an Intel(R) Core(TM) i7-6850K 3.60Hz CPU. Moreover, we apply eight Perm engines to the 1D convolution, which shows a 17.25x speedup over the software implementation.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124839454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Design and manufacture power pre-amplifier module for transmitter of ground station at S-band s波段地面站发射机功率前置放大模块的设计与制作

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2020-12-08 DOI: 10.1109/APCCAS50809.2020.9301712

H. Bui, C. D. Tran, X. Le, G. Bach

引用次数: 1