Proceedings of the 17th ACM International Symposium on Nanoscale Architectures最新文献_第2页

Exploiting the Third Dimension: Stackable Quantum-dot Cellular Automata 利用第三维度:可堆叠的量子点元胞自动机

Proceedings of the 17th ACM International Symposium on Nanoscale Architectures Pub Date : 2022-12-07 DOI: 10.1145/3565478.3572529

Willem Lambooy, Marcel Walter, R. Wille

{"title":"Exploiting the Third Dimension: Stackable Quantum-dot Cellular Automata","authors":"Willem Lambooy, Marcel Walter, R. Wille","doi":"10.1145/3565478.3572529","DOIUrl":"https://doi.org/10.1145/3565478.3572529","url":null,"abstract":"The exponential growth of transistor density in integrated circuits is doomed to fail at the limits of physics in the foreseeable future. Quantum-dot Cellular Automata (QCA) is a post-CMOS contestant from the emerging Field-coupled Nanocomputing (FCN) paradigm which offers computations with tremendously low power dissipation. Recent physical accomplishments in this area also motivated the developments of corresponding design automation methods. However, although the higher integration density of QCA makes this technology a promising candidate for stacked, i. e. cuboid-like, chip architectures, all design automation solutions proposed thus far are limited to 2-dimensional architectures only. This work showcases the potential when the third dimension is additionally utilized. To this end, we must overcome certain obstacles for which corresponding solutions are proposed. Case studies on important regular structures such as bitwise AND/OR, binary adders, or multiplexers---for which we provide automatic generation scripts---confirm that exploiting the third dimension in this fashion yields a prodigious reduction in area occupation and cell count, differing by several orders of magnitude compared to the state of the art.","PeriodicalId":125590,"journal":{"name":"Proceedings of the 17th ACM International Symposium on Nanoscale Architectures","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125947808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

HEADiv: A High-accuracy Energy-efficient Approximate Divider with Error Compensation 具有误差补偿的高精度节能近似除法器

Proceedings of the 17th ACM International Symposium on Nanoscale Architectures Pub Date : 2022-12-07 DOI: 10.1145/3565478.3572324

Hanghang Wang, Ke Chen, Bi Wu, Chenghua Wang, Weiqiang Liu, Fabrizio Lombardi

{"title":"HEADiv: A High-accuracy Energy-efficient Approximate Divider with Error Compensation","authors":"Hanghang Wang, Ke Chen, Bi Wu, Chenghua Wang, Weiqiang Liu, Fabrizio Lombardi","doi":"10.1145/3565478.3572324","DOIUrl":"https://doi.org/10.1145/3565478.3572324","url":null,"abstract":"The circuit complexity of dividers is more considerable than the basic arithmetic units like adders and multipliers. However, the performance of the divider has a significant impact on the system performance, leading to degradation if not appropriately implemented. As a promising design methodology, approximate computing has demonstrated its effectiveness in reducing power consumption and improving performance with good-enough accuracy. This paper proposes an approximate divider HEADiv based on Taylor expansion with error compensation to reduce hardware consumption. The proposed approximate divider is evaluated and analyzed using error and hardware metrics. Compared to other state-of-the-art approximate divider designs, the proposed approximate divider showed 70% and 45% improvement in accuracy for 8-bit and 16-bit dividers, respectively. Besides, the proposed 16-bit approximate divider reduced the area and power consumption by 9% and 42%, respectively. Finally, the experiments illustrate that the proposed approximate divider can improve the PSNR by up to 55% in image processing applications.","PeriodicalId":125590,"journal":{"name":"Proceedings of the 17th ACM International Symposium on Nanoscale Architectures","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122344393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Integrated Control Addressing Circuits for a Surface Code Quantum Computer in Silicon 硅表面码量子计算机的集成控制寻址电路

Proceedings of the 17th ACM International Symposium on Nanoscale Architectures Pub Date : 2022-12-07 DOI: 10.1145/3565478.3572541

Rubaya Absar, Zach D. Merino, H. Elgabra, Xuesong Chen, J. Baugh, Lan Wei

引用次数: 0

An In-memory Booth Multiplier Based on Non-volatile Memory for Neural Network Applications 一种基于非易失性存储器的神经网络应用内存倍增器

Proceedings of the 17th ACM International Symposium on Nanoscale Architectures Pub Date : 2022-12-07 DOI: 10.1145/3565478.3572534

Jiayao Wu, Yijiao Wang, Zhi Yang, Kuiqing He, Pengxu Wang, Weisheng Zhao

引用次数: 0

Efficient Multi-Path Signal Routing for Field-coupled Nanotechnologies 场耦合纳米技术的高效多径信号路由

Proceedings of the 17th ACM International Symposium on Nanoscale Architectures Pub Date : 2022-12-07 DOI: 10.1145/3565478.3572539

Marcel Walter, R. Wille

{"title":"Efficient Multi-Path Signal Routing for Field-coupled Nanotechnologies","authors":"Marcel Walter, R. Wille","doi":"10.1145/3565478.3572539","DOIUrl":"https://doi.org/10.1145/3565478.3572539","url":null,"abstract":"Establishing itself among the vanguard of beyond-CMOS candidates, Field-coupled Nanocomputing (FCN) has advanced in recent times due to fabrication breakthroughs of Silicon Dangling Bonds (SiDBs). At the foundation of these breakthroughs, experimental demonstrations showcase the feasibility of FCN logic components and wire segment implementations at the physical limits of scaling. However, automatic design methods for this highly-promising technology remain scarce, as they are impeded by the necessity to conform to particular constraints that differ from those in CMOS technologies. Previously proposed approaches are restricted by their inability to overcome scalability limitations and/or their failure to generate results of adequate quality. In this work, we aim to improve this state of the art by addressing the epicenter of performance inadequacy and proposing a distinctive multi-path FCN routing algorithm that is explicitly adjusted to the design constraints dictated by FCN technologies. The resulting approach can be parameterized to generate signal routings for almost arbitrary FCN placements or, in case this is impossible, pinpoint the designer to the unsatisfied connections. Experimental evaluations confirm these abilities on an established benchmark set and demonstrate a runtime advantage of several orders of magnitude over a state-of-the-art physical design algorithm.","PeriodicalId":125590,"journal":{"name":"Proceedings of the 17th ACM International Symposium on Nanoscale Architectures","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130939649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Approximate computation based on NAND-SPIN MRAM for CNN on-chip training 基于NAND-SPIN MRAM的CNN片上训练近似计算

Proceedings of the 17th ACM International Symposium on Nanoscale Architectures Pub Date : 2022-12-07 DOI: 10.1145/3565478.3572537

Zhengyi Hou, Luyao Shi, Bi Wang, Zhaohao Wang

引用次数: 0

Single Cycle XOR (SCXOR) and Stateful n-bit Parallel Adder Implementation Using 2D RRAM Crossbar 单周期异或(SCXOR)和有状态n位并行加法器的二维RRAM Crossbar实现

Proceedings of the 17th ACM International Symposium on Nanoscale Architectures Pub Date : 2022-12-07 DOI: 10.1145/3565478.3572329

Bhanprakash Goswami, M. Suri

{"title":"Single Cycle XOR (SCXOR) and Stateful n-bit Parallel Adder Implementation Using 2D RRAM Crossbar","authors":"Bhanprakash Goswami, M. Suri","doi":"10.1145/3565478.3572329","DOIUrl":"https://doi.org/10.1145/3565478.3572329","url":null,"abstract":"The motivation to find a solution to the Memory Wall problem led the research community to explore non-von-Neumann architectures. Compute In-Memory (CIM) architectures with emerging memory technologies are promising for minimizing data movement. In line with the CIM direction, several logical and arithmetic operations were demonstrated in the literature for maximizing operations per second per watt using the RRAM crossbar. In this work, we propose a novel way of realizing stateful XOR logic using RRAM crossbar memory. The proposed XOR design is free from the operand switching issue, and since it needs cells within a single column of the 2D crossbar, logic cascading with other logic gates in the same column is straightforward. Secondly, we offer a novel data shifting technique between two consecutive RRAM cell columns/rows of the crossbar. Leveraging the proposed methods, we realize a stateful n-bit parallel adder that takes n+3 computation cycles and 5n RRAM cells within the crossbar. With the proposed n-bit parallel adder design for n>3, we obtain a minimum 1.4X speedup compared to the literature without using an increased number of RRAM cells.","PeriodicalId":125590,"journal":{"name":"Proceedings of the 17th ACM International Symposium on Nanoscale Architectures","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122990867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

HSB-GDM: a Hybrid Stochastic-Binary Circuit for Gradient Descent with Momentum in the Training of Neural Networks HSB-GDM:神经网络训练中带动量梯度下降的混合随机二值电路

Proceedings of the 17th ACM International Symposium on Nanoscale Architectures Pub Date : 2022-12-07 DOI: 10.1145/3565478.3572530

Han Li, Heng Shi, Honglan Jiang, Siting Liu

引用次数: 0

Low-cost stochastic number generator based on MRAM for stochastic computing 基于MRAM的低成本随机数生成器

Proceedings of the 17th ACM International Symposium on Nanoscale Architectures Pub Date : 2022-12-07 DOI: 10.1145/3565478.3572545

You Wang, Bi Wu, Hao Cai, Weiqiang Liu

引用次数: 0

Data and Fault Aware Routing Algorithm for NoC Based Approximate Computing 基于NoC近似计算的数据和故障感知路由算法

Proceedings of the 17th ACM International Symposium on Nanoscale Architectures Pub Date : 2022-12-07 DOI: 10.1145/3565478.3572327

Ibrahim Krayem, Romain Mercier, C. Killian, A. Kritikakou, D. Chillet

{"title":"Data and Fault Aware Routing Algorithm for NoC Based Approximate Computing","authors":"Ibrahim Krayem, Romain Mercier, C. Killian, A. Kritikakou, D. Chillet","doi":"10.1145/3565478.3572327","DOIUrl":"https://doi.org/10.1145/3565478.3572327","url":null,"abstract":"Due to transistor shrinking and core number increasing in System-on-Chip (SoC), fault tolerance has become a critical concern. Given the amount of data communications on such architectures, Network-on-Chips (NoCs) lead a crucial role in terms of performance. Even if fault correction approaches have been developed, they cannot efficiently address several permanent faults on NoC, due to their high hardware costs and correction limitations. In parallel, Approximate Computing domain considers applications that can tolerate errors, hence allowing fault mitigation instead of correction. This latter brings the opportunity of low implementation cost techniques to improve the reliability of SoC. In this work, we propose a routing technique which selects a path between cores according to data type and permanent fault positions. Error tolerant data are able to cross faulty paths by using a bit-shuffling error mitigation technique. Critical data circumvent faulty paths or are duplicated and shuffled in case there is no other correct path available. Results show that our routing technique allows to maintain all the communication paths within the NoC for a large amount of permanent errors. To further evaluate the behavior of the proposed technique, we performed a comprehensive analysis of the technique on the packet latency and saturation injection rate with respect to the number of faults and traffic type.","PeriodicalId":125590,"journal":{"name":"Proceedings of the 17th ACM International Symposium on Nanoscale Architectures","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129496635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0