Single Cycle XOR (SCXOR) and Stateful n-bit Parallel Adder Implementation Using 2D RRAM Crossbar

The motivation to find a solution to the Memory Wall problem led the research community to explore non-von-Neumann architectures. Compute In-Memory (CIM) architectures with emerging memory technologies are promising for minimizing data movement. In line with the CIM direction, several logical and arithmetic operations were demonstrated in the literature for maximizing operations per second per watt using the RRAM crossbar. In this work, we propose a novel way of realizing stateful XOR logic using RRAM crossbar memory. The proposed XOR design is free from the operand switching issue, and since it needs cells within a single column of the 2D crossbar, logic cascading with other logic gates in the same column is straightforward. Secondly, we offer a novel data shifting technique between two consecutive RRAM cell columns/rows of the crossbar. Leveraging the proposed methods, we realize a stateful n-bit parallel adder that takes n+3 computation cycles and 5n RRAM cells within the crossbar. With the proposed n-bit parallel adder design for n>3, we obtain a minimum 1.4X speedup compared to the literature without using an increased number of RRAM cells.