Proceedings of the 17th ACM International Symposium on Nanoscale Architectures最新文献_第3页

Hardware Efficiency Stochastic Computing based on Hybrid Spatial Coding 基于混合空间编码的硬件效率随机计算

Proceedings of the 17th ACM International Symposium on Nanoscale Architectures Pub Date : 2022-12-07 DOI: 10.1145/3565478.3572535

Yakun Zhou, Yizhuo Zhou, Jiajun Yan, Jienan Chen

引用次数: 0

Binary Bayesian Neural Networks for Efficient Uncertainty Estimation Leveraging Inherent Stochasticity of Spintronic Devices 利用自旋电子器件固有随机性进行有效不确定性估计的二值贝叶斯神经网络

Proceedings of the 17th ACM International Symposium on Nanoscale Architectures Pub Date : 2022-12-07 DOI: 10.1145/3565478.3572536

Soyed Tuhin Ahmed, Kamal Danouchi, Christopher Münch, G. Prenat, Anghel Lorena, Mehdi B. Tahoori

{"title":"Binary Bayesian Neural Networks for Efficient Uncertainty Estimation Leveraging Inherent Stochasticity of Spintronic Devices","authors":"Soyed Tuhin Ahmed, Kamal Danouchi, Christopher Münch, G. Prenat, Anghel Lorena, Mehdi B. Tahoori","doi":"10.1145/3565478.3572536","DOIUrl":"https://doi.org/10.1145/3565478.3572536","url":null,"abstract":"In the age of automation, machine learning systems for real-time critical decisions in various domains such as autonomous driving are at an all-time high. Predictive uncertainty allows a machine learning system to make more insightful decisions by avoiding blind predictions. Algorithmically, Bayesian neural networks (BayNNs) based on dropout are principled methods for estimating predictive uncertainty in a machine learning application. However, the computational cost and power consumption make the use of BayNNs on embedded hardware unattractive. Hardware accelerators with emerging non-volatile resistive memories (NVMs) such as Magnetic Tunnel Junction (MTJ) in conjunction with quantized models are an interesting option for efficient implementations of such a system. Binary BayNNs are a desirable alternative that can provide predictive uncertainty efficiently by combining the benefits of quantization and hardware acceleration. In this paper, propose for the first time the binary bayesian neural network (BayBNN) using dropout-based approximation, and we leverage the inherent randomness of spin-tronic devices for in-memory Bayesian inference. Our proposed method can detect up-to 100% of the out-of-distribution data, improve inference accuracy by 15% for corrupted data, and ~ 2% for in-distribution data.","PeriodicalId":125590,"journal":{"name":"Proceedings of the 17th ACM International Symposium on Nanoscale Architectures","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125987844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A Multi-Level Simulation of GeH FETs: From Nanomaterial and Device Characteristics to Circuit Performance Optimization GeH场效应管的多级模拟:从纳米材料和器件特性到电路性能优化

Proceedings of the 17th ACM International Symposium on Nanoscale Architectures Pub Date : 2022-12-07 DOI: 10.1145/3565478.3572533

Yiju Zhao, Y. Yoon, Lan Wei

{"title":"A Multi-Level Simulation of GeH FETs: From Nanomaterial and Device Characteristics to Circuit Performance Optimization","authors":"Yiju Zhao, Y. Yoon, Lan Wei","doi":"10.1145/3565478.3572533","DOIUrl":"https://doi.org/10.1145/3565478.3572533","url":null,"abstract":"Here, we demonstrate a multi-level simulation for 2D material-based nanoelectronics, including material parameterization, device simulation, physics-based compact modeling, and circuit benchmark. We perform quantum transport simulations based on the Non-equilibrium Green's Function (NEGF) method to calculate the characteristics of two-dimensional (2D) GeH field-effect transistors (FETs). We have developed a compact model by modifying the original virtual source (VS) model to capture the unique behaviors of 2D-material FETs such as voltage-dependent VS velocity and quantum capacitance. HSPICE circuit simulation is then conducted for circuit analyses and optimization of CMOS digital benchmark circuits. Our simulation results show that energy-delay product can be lowered by 50 times if power supply and threshold voltages are properly engineered. This study not only provides a seamless multi-level simulation process to fill a gap between the properties of nanomaterials and the behavior of circuits based on novel FETs, but also advances in-depth understanding of material, device and circuit in a comprehensive manner. It is expected that the suggested approach could be further extended to a framework for 2D material-device-circuit co-optimization processes.","PeriodicalId":125590,"journal":{"name":"Proceedings of the 17th ACM International Symposium on Nanoscale Architectures","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128826321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Capacity-oriented High-performance NV-TCAM Leveraging Hybrid MRAM Scheme 基于混合MRAM方案的容量导向高性能NV-TCAM

Proceedings of the 17th ACM International Symposium on Nanoscale Architectures Pub Date : 2022-12-07 DOI: 10.1145/3565478.3572315

Didi Zhang, Bi Wu, Haonan Zhu, Weiqiang Liu

{"title":"Capacity-oriented High-performance NV-TCAM Leveraging Hybrid MRAM Scheme","authors":"Didi Zhang, Bi Wu, Haonan Zhu, Weiqiang Liu","doi":"10.1145/3565478.3572315","DOIUrl":"https://doi.org/10.1145/3565478.3572315","url":null,"abstract":"As a special type of memory, Ternary Content Addressable Memory (TCAM) has been widely employed in network routers and various applications that require high speed table lookup. However, the large cell area and high static power consumption of traditional CMOS-based TCAMs have always constrained its advance toward higher capacity. Therefore, many non-volatile memory devices, such as ReRAM, FeFET, and MRAM, are emerging in TCAM designs to address these issues. However, SOT-MRAM devices with ultra-high write speed, low power consumption and small cell area are not effectively utilized in TCAM designs due to their low tunnel magnetoresistance (TMR) ratio, etc. In this work, first, combining the ultra-high performance of SOT-MRAM and the reliability of STT-MRAM, a 4T-3MTJ SOT/STT hybrid NV-TCAM structure with ultra-high integration density is proposed. However, to eliminate the lower match line utilization caused by the low TMR of SOT-MRAM, another highly reliable 7T-3MTJ NV-TCAM structure is proposed. Simulation results show that the proposed two TCAM structures can achieve search speed of 0.4ns and 0.15ns with only 4 and 7 transistors, respectively. While maintaining high performance, their write energy is only 0.133pJ/bit, a maximum reduction of 91.6% over existing TCAM designs. Meanwhile, the array-level simulations prove the great potential of the proposed design in terms of integration density and performance.","PeriodicalId":125590,"journal":{"name":"Proceedings of the 17th ACM International Symposium on Nanoscale Architectures","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133127457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

CryptoLight: An Electro-Optical Accelerator for Fully Homomorphic Encryption CryptoLight:一种全同态加密的光电加速器

Proceedings of the 17th ACM International Symposium on Nanoscale Architectures Pub Date : 2022-11-24 DOI: 10.1145/3565478.3572544

Mengxin Zheng, Qian Lou, Fan Chen, Lei Jiang, Yongxin Zhu

引用次数: 0

Proceedings of the 17th ACM International Symposium on Nanoscale Architectures 第17届ACM纳米架构国际研讨会论文集

Proceedings of the 17th ACM International Symposium on Nanoscale Architectures Pub Date : 1900-01-01 DOI: 10.1145/3565478

引用次数: 0