发布求助
文献互助 智能选刊 最新文献

Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'最新文献

筛选
英文 中文
Fluctuation smoothing scheduling policies for multiple process flow fabrication plants 多工艺流程制造工厂的波动平滑调度策略
Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future' Pub Date : 1995-10-02 DOI: 10.1109/IEMT.1995.526114
D. L. Sohl, P. R. Kumar
{"title":"Fluctuation smoothing scheduling policies for multiple process flow fabrication plants","authors":"D. L. Sohl, P. R. Kumar","doi":"10.1109/IEMT.1995.526114","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526114","url":null,"abstract":"This paper addresses the problem of reducing the mean and variance of cycle time in large multi-process flow reentrant systems by using a modified version of the Fluctuation Smoothing for Mean Cycle Time (FSMCT) scheduling policy. The plant models used in this paper were constructed and distributed by SEMATECH. Three such models are studied in this paper. The work done in this paper is the first look at the feasibility of using the FSMCT policy on multi-process flow systems. The size and complexities of the models used here limited the number of simulations performed in this initial study.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116774630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Development of integrated process control system utilizing neural network for plasma etching 基于神经网络的等离子蚀刻集成过程控制系统的开发
Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future' Pub Date : 1995-10-02 DOI: 10.1109/IEMT.1995.526118
Taek-Beom Koh, S. Cha, K. Woo, Dae-Sik Moon, K. Kwak, HoSeung Chang
{"title":"Development of integrated process control system utilizing neural network for plasma etching","authors":"Taek-Beom Koh, S. Cha, K. Woo, Dae-Sik Moon, K. Kwak, HoSeung Chang","doi":"10.1109/IEMT.1995.526118","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526118","url":null,"abstract":"The purpose of this study is to provide the integrated process control system utilizing neural network modeling, to search for the appropriate choice of control input, and to keep the process output within the desired range in the real etch process. Variations in the process output are classified as the drift and the shift. The drift is caused by a natural noise that changes over a period of time slowly and steadily partly due to the aging of equipment. Although the drift moves the process output away from the target value, its variation is infinitesimal. On the other hand, the shift results in a larger variation due to the various causes and its width is normally greater than that of the drift. Without appropriate procedures, the process output will move away from the target value greatly. Therefore the control strategy is to minimize the process shifts, in which process outputs are measured by monitoring wafers periodically.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116870691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Decomposition algorithms for scheduling semiconductor testing facilities 半导体测试设备调度的分解算法
Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future' Pub Date : 1995-10-02 DOI: 10.1109/IEMT.1995.526115
E. Demirkol, R. Uzsoy, I. M. Ovacik
{"title":"Decomposition algorithms for scheduling semiconductor testing facilities","authors":"E. Demirkol, R. Uzsoy, I. M. Ovacik","doi":"10.1109/IEMT.1995.526115","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526115","url":null,"abstract":"The research described in this paper began in 1988 and is directed at developing effective computerized scheduling procedures for a semiconductor testing facility. To this end we first give a brief overview of the testing process and management goals. We then discuss the performance of a series of different scheduling techniques for this problem, beginning with local dispatching rules that use very limited information through more complex dispatching procedures incorporating local optimization and look-ahead capabilities, culminating in a series of decomposition procedures that take a global view of the test area while making scheduling decisions. Our computational experiments indicate that exploiting the real-time factory status information available in existing factory automation systems can result in significant improvements in shop performance. We conclude the paper with a summary and a discussion of future research directions.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117180003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Estimating tools to support multi-path agility in electronics manufacturing 支持电子制造中多路径敏捷性的评估工具
Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future' Pub Date : 1995-10-02 DOI: 10.1109/IEMT.1995.526088
R. Graves, A. Agrawal, K. Haberle
{"title":"Estimating tools to support multi-path agility in electronics manufacturing","authors":"R. Graves, A. Agrawal, K. Haberle","doi":"10.1109/IEMT.1995.526088","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526088","url":null,"abstract":"Electronics manufacturing will increasingly require shorter cycle times for product development and manufacturing, lower volumes of identical items, increased customization, higher quality, and closer coupling among suppliers, customers and manufacturers. This trend is being driven by the demands of the global marketplace as customers demand newer, more compact, lower cost, and higher quality products in shorter concept-to-market intervals. This increased emphasis on achieving highly adaptive manufacturing to reduce manufacturing costs and to better utilize US manufacturing capacity over the future horizon has led to a critical focus on agile manufacturing as a strategy to achieve these goals. Methods for estimating production cost in different environments (along with a conceptual extension to cycle time) that exist in present day systems are discussed.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121580370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
An overview of manufacturing BGA technology 制造BGA技术概述
Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future' Pub Date : 1995-10-02 DOI: 10.1109/IEMT.1995.526200
Joel Mearig, B. Goers
{"title":"An overview of manufacturing BGA technology","authors":"Joel Mearig, B. Goers","doi":"10.1109/IEMT.1995.526200","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526200","url":null,"abstract":"Ball Grid Array (BGA) technology is one ofthe leading edge technologies in surface mount manufacturing. The driving force behind the advancement of BGA technology is the lead spacing of standard surface mount devices. As lead pitches drop below 20 mil, manufacturing becomes exponentially more difficult. BGA technology provides the same I/O count in the same body size with a significant increase in pitch. Manufacturing BGAs is comparable to standard surface mount device manufacturing. Standard equipment for paste application, placement, reflow and cleaning will work with first generation BGAs. The paper discusses BGA manufacturing using 20 mil SMT manufacturing as a baseline.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"297 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123230585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Dual chip memory package 双芯片存储器封装
Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future' Pub Date : 1995-10-02 DOI: 10.1109/IEMT.1995.526104
Y. Kweon, Seung-Ho Ahn, Hae-Jeong Sohn, Young-hee Song, S. Oh
{"title":"Dual chip memory package","authors":"Y. Kweon, Seung-Ho Ahn, Hae-Jeong Sohn, Young-hee Song, S. Oh","doi":"10.1109/IEMT.1995.526104","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526104","url":null,"abstract":"Today's computer systems require more main memories than before due to the development of heavy-load softwares and the integration of multiple functions in a computer. However, since the computers became portable the sizes of computers are getting smaller. This means that it is necessary to put more memory chips into a limited space of the computers. In order to fulfil above requirement, a new high density package was developed, which looked the same as conventional plastic packages outside, and contained two chips inside, and named the Dual Chip Package (DCP). In packaging two chips in a package outline, chip-on-tape (COT) technology was combined with lead frames. The tape had wiring patterns inside and interconnection tabs along the periphery of the tape. The lead frames for the DCP were prepared by bonding the inner leads of the lead frames to the interconnection tabs of the tapes. Two chips are attached to the top side and the bottom side of the tape, and wire-bonded onto the tape surface. In the chip attachment and wire bonding process, one side of the tape was coated with an epoxy encapsulant to protect the chips during the wire bonding of the other side. After this process, the assembly processes were the same as those of conventional plastic packages. With DCP, it is possible to change the pin configurations of the package by varying the design of the tape. Reliability tests showed that the DCP met JEDEC level 3 requirement in pre-conditioning tests.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124968063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Product integrity assessment using fatigue synthesis for avionics programs 航空电子项目中使用疲劳综合的产品完整性评估
Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future' Pub Date : 1995-10-02 DOI: 10.1109/IEMT.1995.526105
M. Rassaian, D. Pietila
{"title":"Product integrity assessment using fatigue synthesis for avionics programs","authors":"M. Rassaian, D. Pietila","doi":"10.1109/IEMT.1995.526105","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526105","url":null,"abstract":"The thermo-mechanical integrity of an electronics assembly is strongly affected by the attachment method used between functional components and the printed wiring board. The use of solder as an interconnect medium is the most common method in use today. In most applications, solder is required to serve multiple functions including electrical, thermal, and structural connection. Repetitive loads caused by thermal cycling and vibrations result in cyclical thermo-mechanical stresses that often lead to pre-mature fatigue cracking in the solder. Continued exposure to these environments leads to degradation or failure of the solder thereby reducing the hardware's useful life. This paper presents a novel method for predicting the fatigue life of an electronics assembly by analyzing every interconnect using an automated process modeling approach. Modular fatigue based routines, incorporated through a user friendly software tool known as FSAP (Fatigue Synthesis for Avionics Programs), facilitate concurrent design development and optimization relative to the hardware's thermo-mechanical fatigue response. FSAP integrates the global effects from specific usage environments with the detailed design and process features associated with the electronics assembly. An application of FSAP along with comprehensive model validation results from accelerated fatigue life testing is presented for a variety of common interconnect configurations including leaded and non-leaded surface mount components and hybrid/MCM packages.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114275651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Ericsson's VLSI mini-fab strategy; low volume VLSI fab to ensure short time to market for Ericsson telecom systems and products 爱立信的VLSI迷你晶圆厂战略;低容量VLSI工厂，以确保爱立信电信系统和产品的短时间上市
Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future' Pub Date : 1995-10-02 DOI: 10.1109/IEMT.1995.526207
Kurt-Ingvar Engde
{"title":"Ericsson's VLSI mini-fab strategy; low volume VLSI fab to ensure short time to market for Ericsson telecom systems and products","authors":"Kurt-Ingvar Engde","doi":"10.1109/IEMT.1995.526207","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526207","url":null,"abstract":"Ericsson adopted a rather different approach when it planned a submicron fab at its Kista site in Sweden. Wafer manufacturing volumes were less important than time factors, since the principal role of the fab is to reduce the design and manufacturing lead times for the complex ASICs needed in the company's telecommunications products and systems. In this paper, the author describes Ericsson's rather unusual strategy for microelectronics sourcing.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131618648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Modeling the cost of ownership of assembly and inspection 对装配和检验的所有权成本进行建模
Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future' Pub Date : 1995-10-02 DOI: 10.1109/IEMT.1995.526090
D. Dance, Thomas DiFloria, D. Jimenez
{"title":"Modeling the cost of ownership of assembly and inspection","authors":"D. Dance, Thomas DiFloria, D. Jimenez","doi":"10.1109/IEMT.1995.526090","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526090","url":null,"abstract":"This paper will use a manufacturing example to illustrate the impacts of robustness, repeatability, and accuracy on COO. By considering life cycle costs as a function of the total number of good devices manufactured over the equipment life, the COO impact of manufacturing and inspection can be estimated in terms of cost per good unit.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134608525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 48
Metrology control for an advanced 200 mm sub-micron wafer fab 先进的200毫米亚微米晶圆厂的计量控制
Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future' Pub Date : 1995-10-02 DOI: 10.1109/IEMT.1995.526098
S.E. Haider, Faa‐Ching Wang, V. Hegemann, J. Capps, R. Price
{"title":"Metrology control for an advanced 200 mm sub-micron wafer fab","authors":"S.E. Haider, Faa‐Ching Wang, V. Hegemann, J. Capps, R. Price","doi":"10.1109/IEMT.1995.526098","DOIUrl":"https://doi.org/10.1109/IEMT.1995.526098","url":null,"abstract":"The advent of sub-micron technology in semiconductor device fabrication has placed a greater emphasis on calibration control of metrology instruments. As device dimensions shrink, accuracy requirements for such instruments is gaining more importance. This paper will discuss the initial set-up methodology during start-up and the control procedures for routine maintenance of metrology instruments in our advanced sub-micron wafer fab. A methodical approach to determining systematic error associated with metrology instruments, using the concepts of tool accuracy, gauge repeatability and reproducibility is presented. Start-up and routine monitoring results for certain metrology instruments such as ellipsometers, scanning electron microscopes, and particle detectors is presented to illustrate our approach.","PeriodicalId":123707,"journal":{"name":"Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121960755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信