发布求助
文献互助 智能选刊 最新文献

2007 7th International Conference on ASIC最新文献

筛选
英文 中文
Adaptive automatic gain control using hybrid gamma parameters for frame-based OFDM receivers 基于帧的OFDM接收机的混合参数自适应自动增益控制
2007 7th International Conference on ASIC Pub Date : 2007-10-01 DOI: 10.1109/ICASIC.2007.4415754
Xiaoqui Wang, Yong Hei, Xuan Zhou, Yumei Zhou
{"title":"Adaptive automatic gain control using hybrid gamma parameters for frame-based OFDM receivers","authors":"Xiaoqui Wang, Yong Hei, Xuan Zhou, Yumei Zhou","doi":"10.1109/ICASIC.2007.4415754","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415754","url":null,"abstract":"Automatic gain control (AGC) is very essential to frame-based orthogonal frequency division multiplexing (OFDM) receivers, because the significant features of OFDM signals are large dynamic range and high Peak-to-Average power Ratio (PAR). This paper proposes an adaptive strategy, which employs flexible gain compensation scheme with hybrid gamma parameters to improve the convergence speed and at the same time maintains the stability of AGC circuits. In order to find the adaptive parameter-changing-point, a new scheme employing a programmable absolute power deviation reference is introduced. At the same time a number of 1-bit buffers are added to reduce the amount of jitter during the gain tracking process. Finally, the performance of the proposed adaptive AGC strategy is discussed by simulation.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128360358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Mixed bus width architecture for low cost AES VLSI design 用于低成本AES VLSI设计的混合总线宽度架构
2007 7th International Conference on ASIC Pub Date : 2007-10-01 DOI: 10.1109/ICASIC.2007.4415765
Yibo Fan, Jidong Wang, T. Ikenaga, S. Goto
{"title":"Mixed bus width architecture for low cost AES VLSI design","authors":"Yibo Fan, Jidong Wang, T. Ikenaga, S. Goto","doi":"10.1109/ICASIC.2007.4415765","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415765","url":null,"abstract":"With the increase of security problem, AES is widely used in a lot of secure systems. For some low data throughput applications, low cost design is more attractive than high speed design. In this paper, low cost hardware architecture for AES algorithm is proposed. Mixed bus width architecture is used to reduce hardware cost and shorten critical path. The experimental results show that the lowest hardware cost implementation of AES algorithm is 4678 gates. The corresponding frequency is 80 MHz and the throughput is 51 Mbps. This architecture is very suitable for mid-throughput, low power and low hardware cost systems such as mobile system.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129147055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Complexity reduction for SOPC-based H.264/AVC coder via sum of absolute difference 基于sopc的H.264/AVC编码器的绝对差和复杂度降低
2007 7th International Conference on ASIC Pub Date : 2007-10-01 DOI: 10.1109/ICASIC.2007.4415869
Ruei-Xi Chen, J. Fan
{"title":"Complexity reduction for SOPC-based H.264/AVC coder via sum of absolute difference","authors":"Ruei-Xi Chen, J. Fan","doi":"10.1109/ICASIC.2007.4415869","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415869","url":null,"abstract":"There exist a number of complex encoding techniques which make H.264 video coding much more efficient, such as the adoption of variable block sizes, multiple reference frames, and the consideration of rate-distortion optimization (RDO). However, these techniques come with a price, i.e. considerable increase of complexity due to the introduction of motion estimation (ME) and mode decision in the design of H.264. In this paper, we have proposed a cost-effective complexity reducing coding algorithm for removing H.264 ME redundancy in SOPC-based embedded systems. The loosely coupled accelerators for Avalon switch fabric compliant topology reveal that the potential coder design can achieve the advantages of flexibility and performance in circuit design without incurring much of the design risk.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130309643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Testing methods for integrated circuit of phase locked loops 锁相环集成电路的试验方法
2007 7th International Conference on ASIC Pub Date : 2007-10-01 DOI: 10.1109/ICASIC.2007.4415796
K. Feng, A. Malladi
{"title":"Testing methods for integrated circuit of phase locked loops","authors":"K. Feng, A. Malladi","doi":"10.1109/ICASIC.2007.4415796","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415796","url":null,"abstract":"The conventional integrated circuit phase locked loop (PLL) has few output signals and offers limited testability. In an event where PLL function does not conform to the specifications, it is often hard and time consuming to debug the problems due to limited accessibility of the internal signals. In this paper we propose a testing structure which uses the existing PLL blocks with minimal additional circuitry thus minimizing the area penalty. The VCO (voltage controlled oscillator) frequency range, VCO gain curve, divider operating range and noise contribution can be determined using the proposed method.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126887417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Performance maximized interlayer via planning for 3D ICs 通过规划3D集成电路实现层间性能最大化
2007 7th International Conference on ASIC Pub Date : 2007-10-01 DOI: 10.1109/ICASIC.2007.4415824
Jun Lu, Song Chen, T. Yoshimura
{"title":"Performance maximized interlayer via planning for 3D ICs","authors":"Jun Lu, Song Chen, T. Yoshimura","doi":"10.1109/ICASIC.2007.4415824","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415824","url":null,"abstract":"As the development of semiconductor industry, 3D IC technology is introduced for its advantages in alleviating the interconnect problem coming with decreasing feature size and increasing integrated density. In 3D IC fabrication, one of the key challenges is the vertical connections between different device layers, which can be implemented by interlayer vias. In this paper, we proposed a performance-maximized interlayer via planning method for 3D ICs (multiple device layers), which can be used in the post-floorplanning stage.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130602793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Low jitter design for ring oscillator in Serdes Serdes环形振荡器的低抖动设计
2007 7th International Conference on ASIC Pub Date : 2007-10-01 DOI: 10.1109/ICASIC.2007.4415628
Lei Xiao, Wei Liu, Lianxing Yang
{"title":"Low jitter design for ring oscillator in Serdes","authors":"Lei Xiao, Wei Liu, Lianxing Yang","doi":"10.1109/ICASIC.2007.4415628","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415628","url":null,"abstract":"A new configuration of delay cell used in voltage controlled oscillators is presented. Jitter comparison between source-coupled differential delay cell and the proposed voltage-controlled-oscillator configuration is given. Loop parameter based on low-jitter optimization in PLL is also introduced. A low-jitter 1.25 GHz SerDes is implemented in a 0.35 mum standard 2P3M CMOS process. The result shows that, RJ rms (random jitter) of high speed series output is 2.3 ps (0.0015UI) and RJ (1sigma) is 0.0035 UI. Phase noise measure shows -120 dBc/Hz at 100 kHz.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130651185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A new ESD-aware power amplifier design method 一种新的防静电功率放大器设计方法
2007 7th International Conference on ASIC Pub Date : 2007-10-01 DOI: 10.1109/ICASIC.2007.4415890
X. Guan, Guang Chen, Lin Lin, Xin Wang, Albert Wang, Lee Yang, B. Zhao
{"title":"A new ESD-aware power amplifier design method","authors":"X. Guan, Guang Chen, Lin Lin, Xin Wang, Albert Wang, Lee Yang, B. Zhao","doi":"10.1109/ICASIC.2007.4415890","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415890","url":null,"abstract":"This paper presents a new ESD-aware power amplifier (PA) design method, featuring S-parameter modeling and output impedance re-matching techniques, to achieve ESD+PA full-chip design optimization. The new method is verified using a 5 kV ESD-protected 2.4 GHz PA circuit designed and implemented in a 0.18 mum RFCMOS technology. Experiment shows substantial performance degradation of PA due to ESD effect, which can be recovered by using the new ESD-aware ESD design method.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"6 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120917445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A new fully differential second generation current conveyor 全新全差动第二代电流输送机
2007 7th International Conference on ASIC Pub Date : 2007-10-01 DOI: 10.1109/ICASIC.2007.4415680
W. Chunhua, Z. Qiujing, Zhao Yan, She Zhixing
{"title":"A new fully differential second generation current conveyor","authors":"W. Chunhua, Z. Qiujing, Zhao Yan, She Zhixing","doi":"10.1109/ICASIC.2007.4415680","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415680","url":null,"abstract":"The paper presents a new fully differential second generation current conveyor (FDCCII). In this circuit, the voltage relations between the differential input Y and the differential terminal X can be tuned by the extra bias current. The principle of the circuit is analyzed in detail. The simulation results show that the port characteristics of the proposed FDCCII are satisfied in the frequency range of 0~30 MHz.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116469890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
± 1.2V High frequency four quadrant current multiplier ±1.2V高频四象限电流倍增器
2007 7th International Conference on ASIC Pub Date : 2007-10-01 DOI: 10.1109/ICASIC.2007.4415594
B. Ghanavati, A. Khoei, K. Hadidi
{"title":"± 1.2V High frequency four quadrant current multiplier","authors":"B. Ghanavati, A. Khoei, K. Hadidi","doi":"10.1109/ICASIC.2007.4415594","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415594","url":null,"abstract":"A new high frequency four quadrant current multiplier is presented. The current multiplier uses complementary MOS devices in triode region and exploits the square-law behaviour of saturated MOS transistors. The circuit operates using the supply voltages of plusmn 1.2 V. The cutoff frequency is 1.74 GHz with a total harmonic distortion less than 0.065 % (at 1 MHz). The power dissipation is 1.2 mW.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114822689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Adiabatic tree multipliers using modified booth algorithm 使用改进的booth算法的绝热树乘数
2007 7th International Conference on ASIC Pub Date : 2007-10-01 DOI: 10.1109/ICASIC.2007.4415592
Ling Wang, Jianping Hu, Hong Li
{"title":"Adiabatic tree multipliers using modified booth algorithm","authors":"Ling Wang, Jianping Hu, Hong Li","doi":"10.1109/ICASIC.2007.4415592","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415592","url":null,"abstract":"This paper presents an adiabatic tree multiplier based on modified Booth algorithm. All circuits including Booth encoders, partial product generators, and compressors are realized with DTGAL (dual transmission gate adiabatic logic) circuits. The energy loss of the proposed adiabatic circuits is compared with their corresponding PAL-2N and CMOS implementations. The proposed circuits are verified using the BSIM3V3 models of TSMC 0.18 mum CMOS technology. The power consumption is greatly reduced since the energy transferred to large load capacitances is well recovered.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124074244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信