{"title":"Serdes环形振荡器的低抖动设计","authors":"Lei Xiao, Wei Liu, Lianxing Yang","doi":"10.1109/ICASIC.2007.4415628","DOIUrl":null,"url":null,"abstract":"A new configuration of delay cell used in voltage controlled oscillators is presented. Jitter comparison between source-coupled differential delay cell and the proposed voltage-controlled-oscillator configuration is given. Loop parameter based on low-jitter optimization in PLL is also introduced. A low-jitter 1.25 GHz SerDes is implemented in a 0.35 mum standard 2P3M CMOS process. The result shows that, RJ rms (random jitter) of high speed series output is 2.3 ps (0.0015UI) and RJ (1sigma) is 0.0035 UI. Phase noise measure shows -120 dBc/Hz at 100 kHz.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"57 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Low jitter design for ring oscillator in Serdes\",\"authors\":\"Lei Xiao, Wei Liu, Lianxing Yang\",\"doi\":\"10.1109/ICASIC.2007.4415628\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new configuration of delay cell used in voltage controlled oscillators is presented. Jitter comparison between source-coupled differential delay cell and the proposed voltage-controlled-oscillator configuration is given. Loop parameter based on low-jitter optimization in PLL is also introduced. A low-jitter 1.25 GHz SerDes is implemented in a 0.35 mum standard 2P3M CMOS process. The result shows that, RJ rms (random jitter) of high speed series output is 2.3 ps (0.0015UI) and RJ (1sigma) is 0.0035 UI. Phase noise measure shows -120 dBc/Hz at 100 kHz.\",\"PeriodicalId\":120984,\"journal\":{\"name\":\"2007 7th International Conference on ASIC\",\"volume\":\"57 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 7th International Conference on ASIC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICASIC.2007.4415628\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 7th International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICASIC.2007.4415628","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A new configuration of delay cell used in voltage controlled oscillators is presented. Jitter comparison between source-coupled differential delay cell and the proposed voltage-controlled-oscillator configuration is given. Loop parameter based on low-jitter optimization in PLL is also introduced. A low-jitter 1.25 GHz SerDes is implemented in a 0.35 mum standard 2P3M CMOS process. The result shows that, RJ rms (random jitter) of high speed series output is 2.3 ps (0.0015UI) and RJ (1sigma) is 0.0035 UI. Phase noise measure shows -120 dBc/Hz at 100 kHz.
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