{"title":"Studies on design of micro power consumption E/D NMOS reference source","authors":"Yonggui Hu, G. Hu, Dongmei Zhu, Yun Xu, J. Yu","doi":"10.1109/ICASIC.2007.4415721","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415721","url":null,"abstract":"In this study, a novel micro power dissipation E/D NMOS reference source circuit was presented. The circuit is simple in structure, but is practical. Compared with a traditional BiCMOS band-gap reference source, the micro power dissipation E/D NMOS reference source has a small static current, and eliminates the need of parasitic bipolar transistor and resistor. All you need to do is to add a depletion-mode N-MOSFET process to a conventional P-well process technology. An E/D NMOS reference source circuit has been developed in 2 mum silicon-gate self-aligned CMOS process technology. In the range -55 to 125degC, the static current measured was less than 2 muA, the voltage regulation measured was less than 2mV, and the temperature coefficient measured was less than 100 ppm/degC.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126301854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Class AB low voltage high linearity mixer design","authors":"Zhao Jie, Cheng Jun-ning, Hongguang Qi, Wei Zhen","doi":"10.1109/ICASIC.2007.4415708","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415708","url":null,"abstract":"Traditional Gilbert cell has been widely used in many mixer circuits, this paper designed a down-conversion mixer which concludes class AB transconductor to improve linearity and LC tank to decrease voltage supply. The RF, LO and IF port frequencies are 2.4 GHz, 2.3 GHz and 100 MHz, respectively. With SMIC 0.18 um process, simulation results show -8dBm of P-ldB compression point and 5 dBm of IIP3 and 7.5 dB of conversion gain with -5 dBm LO power under 1.5 V supply voltage.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125716721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"2.4GHz VCO design and tail current analysis","authors":"Yuemei Li, Zheying Li, Bo Li, Chunlei Wang","doi":"10.1109/ICASIC.2007.4415720","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415720","url":null,"abstract":"This paper presents an LC-based oscillator structure of a widely used complementary cross-coupled VCO. This structure can be widely used in wireless communication, optical communication and high-speed A/D converter, even more other ISM systems. Here is the specification: the supply voltage is 3.3 volts, central oscillation frequency is 2.4 GHz, the tuning range is 21% or so, the power consumption is low, and the phase noise is low enough to meet the DCS-1800 standard. Two prototypes are designed: one uses PMOS current mirror, the other uses NMOS current mirror. Then a comparison is made between the two, and a conclusion is reached on how the tail current affects the whole performance of VCO.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122011215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design and implementation of a high-speed reconfigurable multiplier","authors":"Wei Li, Z. Dai, Tao Meng, Qiao Ren","doi":"10.1109/ICASIC.2007.4415596","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415596","url":null,"abstract":"On the basis of analyzing the theory of multiplication operation in block ciphers and modular multiplication algorithms of different operation width, this paper present a high-speed reconfigurable multiplier, which can be reconfigured to perform 16-bit, 32-bit multiplication and modulo 216+1 multiplication operation, and then optimize each critical block. The design is realized using Altera's FPGA. Synthesis, placement and routing of reconfigurable multiplier have accomplished on 0.18 mum SMIC technology. The result proves that the propagation time of the critical path is 2.84 ns. The reconfigurable multiplier is able to achieve relatively high performance in the block cipher algorithms processing.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127910083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"VLSI design for de-blocking filter of H.264 decoder","authors":"Shuang Zhao, Chao Lu, Xiaofang Zhou, Hao Min, Dian Zhou","doi":"10.1109/ICASIC.2007.4415748","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415748","url":null,"abstract":"De-blocking filter as the output of H.264 decoder affects the speed and throughput of the decoder directly. Based on the fact that the de-blocking filter applied in main profile is demanded more in speed and throughput than in area and consumption, this paper put forward a new structure for de-blocking filter system as well as the most timing cost edge filtering according to the filter algorithm. This circuit is implemented with Xilinx Vertex4 XC4VSX35, and the simulation result indicates this structure is more efficient in area and speed to some degree.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121756581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"K-5 Challenges for consumer electronics for the 21st century","authors":"S. Leibson","doi":"10.1109/ICASIC.2007.4415548","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415548","url":null,"abstract":"CE products now drive the electronic industry's development. (It was previously driven by military programs after World War II, mainframes and minicomputers in the 1950s through the 1970s, and the Personal Computer in the 1980s and 1990s). CE products demand high performance, low cost, and low power consumption. These requirements stress every aspect of design from the circuit to the system level. The tallest technological hurdles lie ahead.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"154 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132517119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. X. Tang, M. H. Tang, F. Yang, J. J. Zhang, Yi Chun Zhou, X. J. Zheng
{"title":"Modeling of temperature characteristics for metal-ferroelectric-insulator-semiconductor devices","authors":"J. X. Tang, M. H. Tang, F. Yang, J. J. Zhang, Yi Chun Zhou, X. J. Zheng","doi":"10.1109/ICASIC.2007.4415813","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415813","url":null,"abstract":"Modeling of temperature characteristics for metal-ferroelectric-insulator-semiconductor devices is given in detail in this paper. Based on the Miller model, the polarization, the electric field in ferroelectric layer, surface potential, and drain-to-source current with gate voltage are investigated over a wide temperature range from 300 K to 600 K. From the model results, for the first time, we find that the semiconductor substrate can lead to the ferroelectric imprint under different temperatures, and there exists a zero-temperature-coefficient bias point in the transfer characteristic curves as conventional metal-oxide-semiconductor devices.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130057520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design of a broadband LNA for TV tuner","authors":"Huang Shi-zhen, Z. Wen-long, Lin Wei","doi":"10.1109/ICASIC.2007.4415712","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415712","url":null,"abstract":"This paper described the design of a broadband LNA for TV tuner. The LNA uses two stage structures to achieve trade off of output impedance match and gain. In order to reduce the NF of the amplifier, noise canceling principle is adopted to cancel the noise. The simulation result shows that, in operation bandwidth 48 MHz~860 MHz, the gain is 24 dB, Noise figure is 3 dB, input impedance and output impedance match are also good.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134077851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Power management by brain emotional learning algorithm","authors":"M. Samadi, A. Afzali-Kusha, C. Lucas","doi":"10.1109/ICASIC.2007.4415571","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415571","url":null,"abstract":"Nowadays having the most energy efficiency is desirable in its own right from both economical and environmental points of view. Dynamic power management is a system level solution for reducing the consumed energy with putting off unused parts of the system and putting them on in an efficient time. The Emotional Learning Algorithm has been introduced to show the effect of emotions as well known stimuli in the quick and almost satisfying decision making in human. The remarkable properties of emotional learning, low computational complexity and fast training, and its simplicity in multi objective problems has made it a powerful methodology in real time control and decision systems, where the gradient based methods and evolutionary algorithms are hard to be used due to their high computational complexity. Recently the emotional approach has been successfully used to obtain multiple objectives in prediction problems of real world phenomena. At first we introduce methods of dynamic power management and then a new method based on BELBIC would be explained. The simulation results show that this method has a high efficiency in various systems.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131052856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Meng-Fan Chang, D. Kwai, Su-Meng Yang, Yung-Fa Chou, Ping-Cheng Chen
{"title":"Experiments on reducing standby current for compilable SRAM using hidden clustered source line control","authors":"Meng-Fan Chang, D. Kwai, Su-Meng Yang, Yung-Fa Chou, Ping-Cheng Chen","doi":"10.1109/ICASIC.2007.4415810","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415810","url":null,"abstract":"This work develops a hidden clustered source line control (HCSLC) technique to reduce the standby current of an embedded SRAM with zero area overhead. The HCSLC scheme utilizes meshed multiple source line control to reduce the fluctuations of virtual ground voltages that are caused by IR drops and process variations. A clustered device-hidden layout scheme is employed to produce compact SRAM layout and attenuate the effects of location/direction-dependent process variations on source line control circuits. A 512 Kb HCSLC SRAM testchip was fabricated using the 0.18 um CMOS process. The HCSLC SRAM achieves 69%~77% reductions of standby current for various processes, supply voltages and temperatures (PVT). The data retention voltage in sleep mode is 0.1 V~0.15 V higher than that in normal mode for the HCSLC SRAM.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133500173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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