ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design最新文献_第4页

Dynamic Thermal Clock Skew Compensation using Tunable Delay Buffers 动态热时钟偏差补偿使用可调延迟缓冲器

ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design Pub Date : 2006-10-04 DOI: 10.1145/1165573.1165612

A. Chakraborty, K. Duraisami, A. Sathanur, P. Sithambaram, L. Benini, A. Macii, E. Macii, M. Poncino

{"title":"Dynamic Thermal Clock Skew Compensation using Tunable Delay Buffers","authors":"A. Chakraborty, K. Duraisami, A. Sathanur, P. Sithambaram, L. Benini, A. Macii, E. Macii, M. Poncino","doi":"10.1145/1165573.1165612","DOIUrl":"https://doi.org/10.1145/1165573.1165612","url":null,"abstract":"The thermal gradients existing in high-performance circuits may significantly affect their timing behavior, in particular by increasing the skew of the clock net and/or altering hold/setup constraints, possibly causing the circuit to operate incorrectly. The knowledge of the spatial distribution of temperature can be used to properly design a clock network that is able to compensate such thermal non-uniformities. However, re-design of the clock network is effective only if temperature distribution is stationary, i.e., does not change over time. In this work, we specifically address the problem of dynamically modifying the clock tree in such a way that it can compensate for temporal variations of temperature. This is achieved by exploiting the buffers that are inserted during the clock network generation, by transforming them into tunable delay elements. Temperature-induced delay variations are then compensated by applying the proper tuning to the tunable buffers, which is computed off-line and, stored in a tuning table inserted in the design. We propose an algorithm to minimize the number of inserted tunable buffers, as well as their tunable range (which directly relates to complexity). Results show that clock skew is kept within original bounds with minimum area and power penalty. The maximum increase in power is 23.2% with most benchmarks exhibiting less than 5% increase in power","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114153677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 78

A Low-Power Active Substrate-Noise Decoupling Circuit with Feedforward Compensation for Mixed-Signal SoCs 一种用于混合信号soc的具有前馈补偿的低功耗有源衬底噪声解耦电路

ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design Pub Date : 2006-10-04 DOI: 10.1145/1165573.1165649

Song Guo, Hoi Lee

引用次数: 2

Analysis of Super Cut-off Transistors for Ultralow Power Digital Logic Circuits 用于超低功耗数字逻辑电路的超级截止晶体管分析

ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design Pub Date : 2006-10-04 DOI: 10.1145/1165573.1165577

A. Raychowdhury, Xuanyao Fong, Qikai Chen, K. Roy

引用次数: 13

A Novel Approach for Variation Aware Power Minimization during Gate Sizing 栅极尺寸变化感知功率最小化的新方法

ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design Pub Date : 2006-10-04 DOI: 10.1145/1165573.1165614

V. Mahalingam, N. Ranganathan, J. Harlow

{"title":"A Novel Approach for Variation Aware Power Minimization during Gate Sizing","authors":"V. Mahalingam, N. Ranganathan, J. Harlow","doi":"10.1145/1165573.1165614","DOIUrl":"https://doi.org/10.1145/1165573.1165614","url":null,"abstract":"Increasing dominance of process variations in the nanometer designs is posing significant challenges for circuit design and optimization. The variations in parameters such as channel length and the gate oxide thickness impacts circuit delay and power. In this paper, we propose a new gate sizing algorithm using fuzzy mathematical programming (FMP) in which the uncertainty due to process variations is modeled using fuzzy numbers. The variations in gate delay, which is a function of gate sizes and the fan-outs of the gate, are represented using triangular fuzzy numbers with linear membership functions. The variation aware gate sizing problem is formulated as a fuzzy mathematical program to perform a delay constrained power minimization in the presence of variations. Initially, a deterministic optimization is performed by fixing the fuzzy parameters to the worst and the average case values and the results are used to convert the fuzzy optimization problem into a crisp non-linear problem which is then solved using a non-linear optimization solver. The above model with delay and power as constraints, maximizes the robustness, i.e., the variation resistance of the circuit and thus the yield. The proposed approach was tested on ISCAS'85 benchmarks and the results were validated for timing yield using Monte-Carlo simulations. The fuzzy approach yields significantly better results compared to stochastic programming based gate sizing approach with a comparable runtime","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"1997 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121073678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Power Phase Variation in a Commercial Server Workload 商业服务器工作负载中的功率相位变化

ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design Pub Date : 2006-10-04 DOI: 10.1145/1165573.1165656

W. Bircher, L. John

引用次数: 6

Reducing Idle Mode Power in Software Defined Radio Terminals 降低软件无线电终端的空闲模式功率

ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design Pub Date : 2006-10-04 DOI: 10.1145/1165573.1165597

Hyunseok Lee, T. Mudge, C. Chakrabarti

引用次数: 4

Energy-efficient Motion Estimation using Error-Tolerance 基于容错的节能运动估计

ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design Pub Date : 2006-10-04 DOI: 10.1145/1165573.1165599

G. Varatkar, Naresh R Shanbhag

引用次数: 75

Reducing Cache Traffic and Energy with Macro Data Load 利用宏观数据负载减少缓存流量和能量

ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design Pub Date : 2006-10-04 DOI: 10.1145/1165573.1165608

Lei Jin, Sangyeun Cho

引用次数: 15

Independent Front-end and Back-end Dynamic Voltage Scaling for a GALS Microarchitecture GALS微架构的独立前端和后端动态电压缩放

ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design Pub Date : 2006-10-04 DOI: 10.1145/1165573.1165586

G. Magklis, P. Chaparro, José González, Antonio González

引用次数: 29

Synchronization-Driven Dynamic Speed Scaling for MPSoCs 同步驱动的mpsoc动态速度缩放

ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design Pub Date : 2006-10-04 DOI: 10.1145/1165573.1165655

M. Loghi, M. Poncino, L. Benini

引用次数: 5