{"title":"Analysis and Modeling of Subthreshold Leakage of RT-Components under PTV and State Variation","authors":"D. Helms, Günter Ehmen, W. Nebel","doi":"10.1145/1165573.1165628","DOIUrl":"https://doi.org/10.1145/1165573.1165628","url":null,"abstract":"In this work we present a SPICE-based RTL subthreshold leakage model analyzing components built in 70nm technology. We present a separation approach regarding inter- and intra-die threshold variations, temperature, supply-voltage, and state dependence. The body-effect and differences between NMOS and PMOS introduce a leakage state dependence of one order of magnitude (Mukhopadhyay, 2003). We show that the leakage of RT-components still shows state dependencies between 20% and 80%. A leakage model not regarding the state can never be more accurate than this. The proposed state aware model has an average error of 6.7% for the RT-components analyzed","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132470205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Low-power Fanout Optimization Using MTCMOS and Multi-Vt Techniques","authors":"B. Amelifard, F. Fallah, Massoud Pedram","doi":"10.1145/1165573.1165652","DOIUrl":"https://doi.org/10.1145/1165573.1165652","url":null,"abstract":"This paper addresses the problem of low-power fanout optimization. We show that due to neglecting short-circuit current, previous analytical techniques proposed to optimize the area of a fanout tree may result in excessive power consumption. This show to achieve a low-power fanout tree, an accurate power consumption model should be used as the objective function. Moreover, we propose an efficient method to minimize the total power consumption of a fanout tree by using MTCMOS and multi-Vt techniques. Experimental results show that depending on the activity factor of the circuit, the proposed technique can reduce the power consumption of the fanout tree 18% to 45%","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128335635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Qinru Qiu, Qing Wu, Daniel J. Burns, Douglas J. Holzhauer
{"title":"Lifetime Aware Resource Management for Sensor Network Using Distributed Genetic Algorithm","authors":"Qinru Qiu, Qing Wu, Daniel J. Burns, Douglas J. Holzhauer","doi":"10.1145/1165573.1165618","DOIUrl":"https://doi.org/10.1145/1165573.1165618","url":null,"abstract":"In this work we consider lifetime-aware resource management for sensor network using distributed genetic algorithm (GA). Our goal is to allocate different detection methods to different sensor nodes in the way such that the required detection probability can be achieved while the network lifetime is maximized. The contribution of this paper is twofold. Firstly, the resource management problem is formulated as a constraint optimization problem and is solved using a distributed GA. Secondly, empirical analysis results are provided that reveals the relationship between the configuration parameters and the quality of the search. A regression model is designed to estimate the runtime of the distributed GA given the configuration parameters. The model is utilized to find energy efficient configurations of the algorithm","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128769360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Sub-Threshold Design: The Challenges of Minimizing Circuit Energy","authors":"B. Calhoun, Alice Wang, N. Verma, A. Chandrakasan","doi":"10.1145/1165573.1165661","DOIUrl":"https://doi.org/10.1145/1165573.1165661","url":null,"abstract":"In this paper, we identify the key challenges that oppose sub-threshold circuit design and describe fabricated chips that verify techniques for overcoming the challenges","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131256404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"SmartSaver: Turning Flash Drive into a Disk Energy Saver for Mobile Computers","authors":"Feng Chen, Song Jiang, Xiaodong Zhang","doi":"10.1145/1165573.1165674","DOIUrl":"https://doi.org/10.1145/1165573.1165674","url":null,"abstract":"In a mobile computer the hard disk consumes a considerable amount of energy. Existing dynamic power management policies usually take conservative approaches to save disk energy, and disk energy consumption remains a serious issue. Meanwhile, the flash drive is becoming a must-have portable storage device for almost every laptop user on travel. In this paper, we propose to make another highly desired use of the flash drive - saving disk energy. This is achieved by using the flash drive as a standby buffer for caching and prefetching disk data. Our design significantly extends disk idle times with careful and deliberate consideration of the particular characteristics of the flash drive. Trace-driven simulations show that up to 41% of disk energy can be saved with a relatively small amount of data written to the flash drive","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122309073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Singh, R. Senger, D. Sylvester, Richard B. Brown, K. Nowka
{"title":"A Dual-VDD Boosted Pulsed Bus Technique for Low Power and Low Leakage Operation","authors":"H. Singh, R. Senger, D. Sylvester, Richard B. Brown, K. Nowka","doi":"10.1145/1165573.1165591","DOIUrl":"https://doi.org/10.1145/1165573.1165591","url":null,"abstract":"In this paper, we propose a new dual-VDD bus technique that is well suited for low power operation. This technique adapts a static pulsed bus architecture to use dual-VDD power supplies. During quiescent periods, the bus system idles at the lower of the two VDD supplies, thereby lowering static power dissipation. When actively transitioning, the inverters in the bus system are temporarily boosted to the higher VDD supply to provide the needed drive strength for performance. Since the VDD boosting is done in a pulsed manner, the bus system is in a high VDD state only when required, ensuring lower power operation without sacrificing performance. This technique yields up to a 50% reduction in total power over traditional static buses and up to a 35% reduction in total power over standard static pulsed buses, with a 12-15% delay improvement","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124496910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hong-Wei Huang, Hsin-Hsin Ho, Ke-Horng Chen, S. Kuo
{"title":"Dithering Skip Modulator with a Novel Load Sensor for Ultra-wide-load High-Efficiency DC-DC Converters","authors":"Hong-Wei Huang, Hsin-Hsin Ho, Ke-Horng Chen, S. Kuo","doi":"10.1145/1165573.1165669","DOIUrl":"https://doi.org/10.1145/1165573.1165669","url":null,"abstract":"Dithering skip mode with a novel load sensor for DC-DC converters is proposed to maintain a high efficiency over a wide load range. Due to the efficiency drop of the transition from the pulse-width modulation (PWM) to pulse-frequency modulation (PFM), a novel dithering skip modulation (DSM) is introduced to smooth the efficiency curve. Importantly, DSM mode can dynamically skip the number of gate driving pulses, which is inverse proportional to load current. Besides, a novel proposed load sensor can automatically select the optimum modulation method from these three modulation methods without an external selection pin. Simulation results shows DSM can maintain the efficiency of converters as high as about 89% over a wide load current range from 3mA to 500mA","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131372984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Novel Dynamic Power Cutoff Technique (DPCT) for Active Leakage Reduction in Deep Submicron CMOS Circuits","authors":"Baozhen Yu, M. Bushnell","doi":"10.1145/1165573.1165627","DOIUrl":"https://doi.org/10.1145/1165573.1165627","url":null,"abstract":"Due to the exponential increase in subthreshold leakage and gate leakage with technology scaling, leakage power is becoming a major fraction of total VLSI chip power in active mode. We present a novel active leakage power reduction technique, called the dynamic power cutoff technique (DPCT). First, the switching window for each gate, during which a gate makes its transitions, is identified by static timing analysis. Then, the circuit is optimally partitioned into different groups based on the minimal switching window (MSW) of each gate. Finally, power cutoff transistors are inserted into each group to control the power connections of that group. Each group is turned on only long enough for a wavefront of changing signals to propagate through that group. Since each gate is only turned on during a small timing window within each clock cycle, this significantly reduces active leakage power. This technique can also save standby leakage and dynamic power. Results on ISCAS'85 benchmark circuits modeled using 70 nm Berkeley predictive models (Cao et al., 2000) show up to 90% active leakage, 99% standby leakage, 54% dynamic power, and 72% total power savings","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"30 15","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113942679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design and Power Management of Energy Harvesting Embedded Systems","authors":"V. Raghunathan, P. Chou","doi":"10.1145/1165573.1165663","DOIUrl":"https://doi.org/10.1145/1165573.1165663","url":null,"abstract":"Harvesting energy from the environment is a desirable and increasingly important capability in several emerging applications of embedded systems such as sensor networks, biomedical implants, etc. While energy harvesting has the potential to enable near-perpetual system operation, designing an efficient energy harvesting system that actually realizes this potential requires an in-depth understanding of several complex tradeoffs. These tradeoffs arise due to the interaction of numerous factors such as the characteristics of the harvesting transducers, chemistry and capacity of the batteries used (if any), power supply requirements and power management features of the embedded system, application behavior, etc. This paper surveys the various issues and tradeoffs involved in designing and operating energy harvesting embedded systems. System design techniques are described that target high conversion and storage efficiency by extracting the most energy from the environment and making it maximally available for consumption. Harvesting aware power management techniques are also described, which reconcile the very different spatio-temporal characteristics of energy availability and energy usage within a system and across a network","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122180172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Robust Multiple-Phase Switched-Capacitor DC-DC, Converter with Digital Interleaving Regulation Scheme","authors":"D. Ma","doi":"10.1145/1165573.1165671","DOIUrl":"https://doi.org/10.1145/1165573.1165671","url":null,"abstract":"An integrated switched-capacitor (SC) DC-DC converter with a digital interleaving regulation scheme is presented. By interleaving the newly-structured charge pump (CP) cells in multiple phases, the input current ripple and output voltage ripple are reduced significantly. The converter exhibits excellent robustness, even when one of the CP cells fails to operate. A fully digital controller is employed with a hysteretic control algorithm. It features dead-beat system stability and fast transient response. Hspice post-layout simulation shows that, with a 1.5 V input power supply, the SC converter accurately provides an adjustable regulated power output in a range of 1.6 to 2.7 V. The maximum output ripple is 40 mV when a full load of 0.54 W is supplied. Transient response of 1.8 mus is observed when the load current switches from half- to full-load (from 100 to 200 mA)","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116580173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}