ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design最新文献

A Low Power SRAM Architecture Based on Segmented Virtual Grounding 一种基于分段虚拟接地的低功耗SRAM结构

ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design Pub Date : 2006-10-04 DOI: 10.1145/1165573.1165635

M. Sharifkhani, M. Sachdev

引用次数: 6

Integrated Solar Energy Harvesting and Storage 集成太阳能收集和储存

ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design Pub Date : 2006-10-04 DOI: 10.1145/1165573.1165580

N. J. Guilar, Albert Chen, Travis Kleeburg, R. Amirtharajah

引用次数: 86

Power-Conscious Configuration Cache Structure and Code Mapping for Coarse-Grained Reconfigurable Architecture 基于功耗意识的配置缓存结构和粗粒度可重构架构的代码映射

ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design Pub Date : 2006-10-04 DOI: 10.1145/1165573.1165646

Yoonjin Kim, Ilhyun Park, Kiyoung Choi, Y. Paek

引用次数: 55

An Efficient Chip-level Time Slack Allocation Algorithm for Dual-Vdd FPGA Power Reduction 一种高效的双vdd FPGA时延分配算法

ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design Pub Date : 2006-10-04 DOI: 10.1145/1165573.1165613

Yan Lin, Yu Hu, Lei He, Vijay Raghunat

引用次数: 5

Dynamic Current Modeling at the Instruction Level 指令级的动态电流建模

ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design Pub Date : 2006-10-04 DOI: 10.1145/1165573.1165596

Jose Rizo-Morente, M. Casas-Sanchez, C. Bleakley

引用次数: 1

A Two-Port SRAM for Real-Time Video Processor Saving 53% of Bitline Power with Majority Logic and Data-Bit Reordering 基于多数逻辑和数据位重排序的实时视频处理器双端口SRAM节省53%的位线功耗

ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design Pub Date : 2006-10-04 DOI: 10.1145/1165573.1165589

H. Fujiwara, K. Nii, J. Miyakoshi, Y. Murachi, Y. Morita, H. Kawaguchi, M. Yoshimoto

引用次数: 14

Adaptive Duty Cycling for Energy Harvesting Systems 能量收集系统的自适应占空循环

ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design Pub Date : 2006-10-04 DOI: 10.1145/1165573.1165616

Jason Hsu, S. Zahedi, A. Kansal, M. Srivastava, V. Raghunathan

{"title":"Adaptive Duty Cycling for Energy Harvesting Systems","authors":"Jason Hsu, S. Zahedi, A. Kansal, M. Srivastava, V. Raghunathan","doi":"10.1145/1165573.1165616","DOIUrl":"https://doi.org/10.1145/1165573.1165616","url":null,"abstract":"Harvesting energy from the environment is feasible in many applications to ameliorate the energy limitations in sensor networks. In this paper, we present an adaptive duty cycling algorithm that allows energy harvesting sensor nodes to autonomously adjust their duty cycle according to the energy availability in the environment. The algorithm has three objectives, namely: (a) achieving energy neutral operation, i.e., energy consumption should not be more than the energy provided by the environment; (b) maximizing the system performance based on an application utility model subject to the above energy-neutrality constraint; and (c) adapting to the dynamics of the energy source at run-time. We present a model that enables harvesting sensor nodes to predict future energy opportunities based on historical data. We also derive an upper bound on the maximum achievable performance assuming perfect knowledge about the future behavior of the energy source. Our methods are evaluated using data gathered from a prototype solar energy harvesting platform and we show that our algorithm can utilize up to 58% more environmental energy compared to the case when harvesting-aware power management is not used","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126553216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 243

Input-specific Dynamic Power Optimization for VLSI Circuits VLSI电路输入特定动态功率优化

ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design Pub Date : 2006-10-04 DOI: 10.1145/1165573.1165630

Fei Hu, V. Agrawal

引用次数: 11

High-Speed Low-Power Frequency Divider with Intrinsic Phase Rotator 带本征相位旋转器的高速低功率分频器

ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design Pub Date : 2006-10-04 DOI: 10.1145/1165573.1165641

S. Henzler, S. Koeppe

引用次数: 1

An Optimal Analytical Solution for Processor Speed Control with Thermal Constraints 热约束下处理器速度控制的最优解析解

ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design Pub Date : 2006-10-04 DOI: 10.1145/1165573.1165643

Ravishankar Rao, S. Vrudhula, C. Chakrabarti, N. Chang

{"title":"An Optimal Analytical Solution for Processor Speed Control with Thermal Constraints","authors":"Ravishankar Rao, S. Vrudhula, C. Chakrabarti, N. Chang","doi":"10.1145/1165573.1165643","DOIUrl":"https://doi.org/10.1145/1165573.1165643","url":null,"abstract":"As semiconductor manufacturing technology scales to smaller device sizes, the power consumption of clocked digital ICs begins to increase. Dynamic voltage and frequency scaling (DVFS) is a well-known technique for conserving energy. Recently, it has also been used to control the CPU temperature as part of dynamic thermal management (DTM) techniques. Most works in these areas assume that the optimum speed profile (for either minimizing energy or maximizing performance) is a constant profile. However, in the presence of thermal constraints, we show that the optimal profile is in general, a time-varying function. We formulate the problem of maximizing the average throughput of a processor over a given time period, subject to thermal and speed constraints, as a problem in the calculus of variations. The variational approach provides a powerful framework for precisely specifying and solving the speed control problem, and allows us to obtain an exact analytical solution. The solution methodology is very general, and works for any convex power model, and simple lumped RC thermal models. The resulting speed profiles were found to consist of up to three segments, of which one of them is a decreasing function of time, and the others are constant. We analyze the effect of different parameters like the initial temperature, thermal capacitance and the maximum rated speed on the nature and the cost of the optimum solution. We also propose a two-speed solution that approximates the optimal speed curve. This solution was found to achieve a performance close to that of the optimum, and is also easier to implement in real processors","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"194 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127122396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 51