一种高效的双vdd FPGA时延分配算法

ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design Pub Date : 2006-10-04 DOI:10.1145/1165573.1165613

Yan Lin, Yu Hu, Lei He, Vijay Raghunat

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引用次数: 5

摘要

为了降低FPGA功耗，最近提出了一种基于线性规划(LP)的时间松弛分配算法EdTLC-LP，用于混合线长的vdd -可编程互连，而不使用vdd级转换器。但是，解决时间空闲分配的LP问题需要很长时间。本文提出了一种基于最小成本网络流的空闲分配算法EdTLC-NW，以减少运行时间。与带功率门控的单Vdd FPGA相比，EdTLC-LP和EdTLC-NW的互连功耗分别降低了52.71%和52.52%。EdTLC-NW的结果与EdTLC-LP一样好，但平均运行速度快8倍。此外，对于更大的电路，EdTLC-NW的加速速度增加了20倍，对于最大的电路

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An Efficient Chip-level Time Slack Allocation Algorithm for Dual-Vdd FPGA Power Reduction

To reduce FPGA power, a linear programming (LP) based time slack allocation algorithm, EdTLC-LP, has been proposed recently for Vdd-programmable interconnects without using Vdd-level converters for mixed wire lengths. However, it takes a long time to solve the LP problem for time slack allocation. In this paper, we develop EdTLC-NW, a slack allocation algorithm based on min-cost network flow to reduce runtime. Compared to single Vdd FPGA with power-gating, EdTLC-LP and EdTLC-NW reduce interconnect power by 52.71% and 52.52%, respectively. EdTLC-NW achieves as good results as EdTLC-LP but runs 8times faster on average. Furthermore, the speedup increases for larger circuits and EdTLC-NW is 20times faster for the largest circuit

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ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design

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