A Two-Port SRAM for Real-Time Video Processor Saving 53% of Bitline Power with Majority Logic and Data-Bit Reordering

H. Fujiwara, K. Nii, J. Miyakoshi, Y. Murachi, Y. Morita, H. Kawaguchi, M. Yoshimoto
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引用次数: 14

Abstract

We propose a low-power two-port SRAM suitable for real-time video processing. In order to minimize discharge power on a read bitline, a majority-logic decides if input data are inverted in a write cycle, so that "1"s are in the majority. In video data, since more significant bits of adjacent pixel data are fortunately lopsided to either "0" or "1" with higher probability, the data bits in the pixels are reordered in each digit group to exploit the majority logic. The speed and area overheads are 4% and 11% in a 90-nm process technology, respectively. The proposed SRAM achieves 53% power reduction on the bitlines, and saves 43% of a total power when considered as an H.264 reconstructed-image memory
基于多数逻辑和数据位重排序的实时视频处理器双端口SRAM节省53%的位线功耗
我们提出了一种适合实时视频处理的低功耗双端口SRAM。为了最小化读位线上的放电功率,多数逻辑决定输入数据是否在写周期中反转,以便“1”占多数。在视频数据中,由于相邻像素数据中更重要的位幸运地以更高的概率向“0”或“1”倾斜,因此像素中的数据位在每个数字组中被重新排序以利用多数逻辑。在90纳米制程技术中,速度和面积开销分别为4%和11%。所提出的SRAM在位线上的功耗降低了53%,在作为H.264重构图像存储器时节省了43%的总功耗
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