发布求助
文献互助 智能选刊 最新文献

ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design最新文献

筛选
英文 中文
Dynamic Thermal Management for MPEG-2 Decoding MPEG-2解码的动态热管理
ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design Pub Date : 2006-10-04 DOI: 10.1145/1165573.1165647
Wonbok Lee, Kimish Patel, Massoud Pedram
{"title":"Dynamic Thermal Management for MPEG-2 Decoding","authors":"Wonbok Lee, Kimish Patel, Massoud Pedram","doi":"10.1145/1165573.1165647","DOIUrl":"https://doi.org/10.1145/1165573.1165647","url":null,"abstract":"In this paper, we propose an effective dynamic thermal management (DTM) scheme for MPEG-2 decoding by allowing some degree of spatiotemporal quality degradation. Given a target MPEG-2 decoding time, we dynamically select either an intra-frame spatial degradation or an inter-frame temporal degradation strategy in order to make sure that the microprocessor chip continues to stay in a thermally safe state of operation, albeit with certain amount of image/video quality loss. For our experiments, we use the MPEG-2 decoder program of MediaBench and modify/combine Wattch and HotSpot for the power and thermal simulations and measurements, respectively. Our experimental results show that we achieve thermally safe state with spatial quality degradation of 0.12 root mean square error (RMSE) and with frame drop rate of 12.5% on average","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124375736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
Modelling Macromodules for High-Level Dynamic Power Estimation of FPGA-based Digital Designs 基于fpga的数字设计高级动态功率估计的宏模块建模
ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design Pub Date : 2006-10-04 DOI: 10.1145/1165573.1165609
A. Reimer, Arne Schulz, W. Nebel
{"title":"Modelling Macromodules for High-Level Dynamic Power Estimation of FPGA-based Digital Designs","authors":"A. Reimer, Arne Schulz, W. Nebel","doi":"10.1145/1165573.1165609","DOIUrl":"https://doi.org/10.1145/1165573.1165609","url":null,"abstract":"We present our approach for a new macromodule power model library which can be used in high-level dynamic power estimation for FPGA technologies. The approach adapts a previously published high-level estimation flow for ASIC technologies. Due to the different architectures (ASIC vs. FPGA) the presented approach builds on an iterative optimization step during the model generation phase","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130915671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Hierarchical Value Cache Encoding for Off-Chip Data Bus 片外数据总线的分层值缓存编码
ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design Pub Date : 2006-10-04 DOI: 10.1145/1165573.1165607
Chung-Hsiang Lin, Chia-Lin Yang, K. King
{"title":"Hierarchical Value Cache Encoding for Off-Chip Data Bus","authors":"Chung-Hsiang Lin, Chia-Lin Yang, K. King","doi":"10.1145/1165573.1165607","DOIUrl":"https://doi.org/10.1145/1165573.1165607","url":null,"abstract":"Off-chip data bus consumes a significant part of system power. Recent works use small caches (value cache) at each side of the off-chip data bus, and transmit cache indexes instead of data values to reduce bus switching activity. A larger VC has a higher VC hit rate, but it also incurs more switching activity on a VC hit. In this paper, we propose the hierarchical VC design concept that provides a good tradeoff between VC capacity and bus switching activity. Our experimental results show that the proposed hierarchical VC design reduces the off-chip data bus energy by 60.2%","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126876784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Logic Circuits Operating in Subthreshold Voltages 在亚阈值电压下工作的逻辑电路
ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design Pub Date : 2006-10-04 DOI: 10.1145/1165573.1165604
J. Nyathi, B. Bero
{"title":"Logic Circuits Operating in Subthreshold Voltages","authors":"J. Nyathi, B. Bero","doi":"10.1145/1165573.1165604","DOIUrl":"https://doi.org/10.1145/1165573.1165604","url":null,"abstract":"In this paper different logic circuit families operating in the subthreshold region are analyzed. Their performance in terms of power and speed are of particular interest. The study complements existing work that has reported static CMOS circuit performance under different body biasing schemes in the subthreshold region. Further it offers assurances on noise margins with scaling going beyond the 100 nm technology node. Simulations have been performed at the 180 nm technology node using a 6 metal layer TSMC process. A tunable body biasing scheme that allows bulk CMOS circuits to operate efficiently at subthreshold as well as above threshold voltages is introduced. The scheme improves a five-stage NAND ring oscillator switching speed 6times better than the static CMOS configuration while dissipating 18% less power","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122664776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Thread-Associative Memory for Multicore and Multithreaded Computing 面向多核和多线程计算的线程关联内存
ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design Pub Date : 2006-10-04 DOI: 10.1145/1165573.1165606
Shuo Wang, Lei Wang
{"title":"Thread-Associative Memory for Multicore and Multithreaded Computing","authors":"Shuo Wang, Lei Wang","doi":"10.1145/1165573.1165606","DOIUrl":"https://doi.org/10.1145/1165573.1165606","url":null,"abstract":"Presented in this paper is the thread-associative memory microarchitecture for multicore and multithreaded processor design. Memory contention among concurrent threads in chip multithreaded processing has become a limiting factor for performance improvement. The proposed thread-associative memory addresses this challenge by incorporating thread-specific information explicitly into on-chip memory hardware. The proposed technique can be utilized at different levels of memory hierarchy. Furthermore, it is not just a technique for performance enhancement but also a solution for energy efficiency. Trace-driven simulations on a 32KB L1 data cache demonstrate 36.6% maximum performance improvement and up to 15.1% total energy reduction, with 20.3% dynamic energy reduction and 9.9% leakage energy reduction","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125255072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Power Efficiency for Variation-Tolerant Multicore Processors 可变容错多核处理器的功率效率
ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design Pub Date : 2006-10-04 DOI: 10.1145/1165573.1165645
J. Donald, M. Martonosi
{"title":"Power Efficiency for Variation-Tolerant Multicore Processors","authors":"J. Donald, M. Martonosi","doi":"10.1145/1165573.1165645","DOIUrl":"https://doi.org/10.1145/1165573.1165645","url":null,"abstract":"Challenges in multicore processor design include meeting demands for performance, power, and reliability. The progression towards deep submicron process technologies entails increasing challenges of process variability resulting in timing instabilities and leakage power variation. This work introduces an analytical approach for ensuring timing reliability while meeting the appropriate performance and power demands in spite of process variation. We validate our analytical model using Turandot to simulate an 8-core PowerPCtrade processor. We first examine a simplified case of our model on a platform running independent multiprogrammed workloads consisting of all 26 of the SPEC 2000 benchmarks. Our simple model accurately predicts the cutoff point with a mean error less than 0.5 W. Next, we extend our analysis to parallel programming by incorporating Amdahl's law in our equations. We use this relation to establish limit properties of power-performance for scaling parallel applications, and validate our findings using 8 applications from the SPLASH-2 benchmark suite","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"346 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133790482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 71
A 0.5-V FD-SOI Twin-Cell DRAM with Offset-Free Dynamic-VT Sense Amplifiers 带无偏置动态vt检测放大器的0.5 v FD-SOI双单元DRAM
ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design Pub Date : 2006-10-04 DOI: 10.1145/1165573.1165602
R. Takemura, K. Itoh, T. Sekiguchi
{"title":"A 0.5-V FD-SOI Twin-Cell DRAM with Offset-Free Dynamic-VT Sense Amplifiers","authors":"R. Takemura, K. Itoh, T. Sekiguchi","doi":"10.1145/1165573.1165602","DOIUrl":"https://doi.org/10.1145/1165573.1165602","url":null,"abstract":"Three DRAM technologies, which are a leakage- and soft-error-free planar-capacitor SOI cell, a data-line shielded twin (2-T) cell array, and an offset-free dynamic-VT sense amplifier suitable for low-voltage mid-point sensing, are presented and evaluated. New noise-generation mechanisms are also shown. Using the experimental data of an ultrathin BOX double-gate fully-depleted SOI MOST, a 1.5-ns cycle-time 65-nm 2-kb subarray was found to be feasible for embedded applications, even at 0.5 V","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134096451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Power Optimization In A Repeater-Inserted Interconnect Via Geometric Programming 基于几何规划的中继器插入互连的功率优化
ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design Pub Date : 2006-10-04 DOI: 10.1145/1165573.1165629
W. Cheung, N. Wong
{"title":"Power Optimization In A Repeater-Inserted Interconnect Via Geometric Programming","authors":"W. Cheung, N. Wong","doi":"10.1145/1165573.1165629","DOIUrl":"https://doi.org/10.1145/1165573.1165629","url":null,"abstract":"We present an innovative geometric programming (GP) approach for minimizing the power dissipation of an interconnect with repeater insertion, subject to delay, bandwidth and area constraints. Repeater sizes and segment lengths are globally optimized in various technology nodes with respect to International Technology Roadmap for Semiconductors (ITRS). Relative power dissipation due to different power components is analyzed. We show that, on average, the power dissipation per unit length can be reduced by over 30% when the timing constraint is relaxed by 5%. The optimum number of repeaters is always given as an integer in our design flow. The relationships between power dissipation and respective design constraints are easily visualized in tradeoff curves. Additional design criteria, such as reliability of the interconnect delay against process variations, are easily incorporated into the optimization","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116415309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A New Technique for Jointly Optimizing Gate Sizing and Supply Voltage in Ultra-Low Energy Circuits 超低能量电路中栅极尺寸和电源电压联合优化的新技术
ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design Pub Date : 2006-10-04 DOI: 10.1145/1165573.1165653
S. Hanson, D. Sylvester, D. Blaauw
{"title":"A New Technique for Jointly Optimizing Gate Sizing and Supply Voltage in Ultra-Low Energy Circuits","authors":"S. Hanson, D. Sylvester, D. Blaauw","doi":"10.1145/1165573.1165653","DOIUrl":"https://doi.org/10.1145/1165573.1165653","url":null,"abstract":"Mobile applications with battery lifetimes on the order of thousands of days have placed stringent energy requirements on circuits. In this paper, we propose a new energy optimization technique for ultra-low energy circuits operating in the sub threshold regime. Our technique uses simultaneous gate sizing and supply voltage scaling to reduce energy. We demonstrate the effectiveness of our technique on benchmark circuits and offer insight on the roles of the timing distribution and wire capacitance in determining the achievable energy reductions","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125668708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Behavioral Modeling of Opamp Gain and Dynamic Effects for Power Optimization of Delta-Sigma Modulators and Pipelined ADCs δ - sigma调制器和流水线adc功率优化的运放增益和动态影响行为建模
ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design Pub Date : 2006-10-04 DOI: 10.1145/1165573.1165651
A. Hamoui, T. Alhajj, M. Taherzadeh‐Sani
{"title":"Behavioral Modeling of Opamp Gain and Dynamic Effects for Power Optimization of Delta-Sigma Modulators and Pipelined ADCs","authors":"A. Hamoui, T. Alhajj, M. Taherzadeh‐Sani","doi":"10.1145/1165573.1165651","DOIUrl":"https://doi.org/10.1145/1165573.1165651","url":null,"abstract":"This paper proposes a simple, yet accurate, analytical model for the effect of opamp gain and dynamics (slew rate and bandwidth) on the transfer function of switched-capacitor (SC) amplifiers and integrators. Furthermore, it demonstrates the detrimental effects of: a) the nonlinear variation in the opamp dc gain; and b) the feedforward transmission of the feedback capacitor, on the harmonic distortion and settling behavior of these SC stages. These effects, typically ignored in the behavioral simulations of SC stages, are analyzed and modeled. Thus, accurate behavioral simulations of DeltaSigma modulators or pipelined analog-to-digital converters (ADCs) can be performed in SIMULINK, using the proposed models for their SC building blocks (integrators or amplifiers). The proposed behavioral models are validated in HSPICE. Behavioral simulation examples are presented to illustrate the importance of such accurate modeling for low-power design","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131504523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信