带无偏置动态vt检测放大器的0.5 v FD-SOI双单元DRAM

ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design Pub Date : 2006-10-04 DOI:10.1145/1165573.1165602

R. Takemura, K. Itoh, T. Sekiguchi

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引用次数: 7

摘要

提出并评价了三种DRAM技术，即无泄漏和软误差的平面电容SOI单元、数据线屏蔽双(2-T)单元阵列和适用于低压中点传感的无偏移动态vt检测放大器。本文还介绍了新的噪声产生机制。利用超薄BOX双栅全耗尽SOI MOST的实验数据，发现即使在0.5 V下，1.5 ns周期时间的65nm 2-kb子阵列也可用于嵌入式应用

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A 0.5-V FD-SOI Twin-Cell DRAM with Offset-Free Dynamic-VT Sense Amplifiers

Three DRAM technologies, which are a leakage- and soft-error-free planar-capacitor SOI cell, a data-line shielded twin (2-T) cell array, and an offset-free dynamic-VT sense amplifier suitable for low-voltage mid-point sensing, are presented and evaluated. New noise-generation mechanisms are also shown. Using the experimental data of an ultrathin BOX double-gate fully-depleted SOI MOST, a 1.5-ns cycle-time 65-nm 2-kb subarray was found to be feasible for embedded applications, even at 0.5 V

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ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design

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