Reducing Idle Mode Power in Software Defined Radio Terminals

Hyunseok Lee, T. Mudge, C. Chakrabarti
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引用次数: 4

Abstract

In this paper, we propose a processor which is optimized for idle mode operation of a software defined radio (SDR) terminal. Since a SDR terminal spends most of its time in the idle mode, reducing the power consumption in this mode directly translates to longer terminal standby time. Workload analysis of idle mode operations of contemporary standards showed that these are dominated by FIR filtering, which can be easily parallelized. This analysis was used in the design of the idle mode processor. The key architectural components are an SIMD unit for the parallel computations that dominate the workload, a conventional scalar unit for the sequential computations, and a control unit which supports efficient data memory access and loop control. The idle mode processor was modeled with Verilog and synthesized using standard cells in 0.13 micron technology. It consumes about 9mW at 1.08V
降低软件无线电终端的空闲模式功率
本文提出了一种针对软件无线电(SDR)终端的空闲工作模式进行优化的处理器。由于SDR终端大部分时间处于空闲模式,因此降低空闲模式下的功耗直接意味着延长终端待机时间。当代标准的空闲模式操作的工作负载分析表明,这些操作主要由FIR滤波控制,可以很容易地并行化。该分析被用于空闲模式处理器的设计。关键的体系结构组件是用于主导工作负载的并行计算的SIMD单元、用于顺序计算的常规标量单元,以及支持高效数据内存访问和循环控制的控制单元。利用Verilog对空闲模式处理器进行建模,并在0.13微米工艺下使用标准细胞进行合成。它在1.08V时消耗约9mW
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