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China., 1991 International Conference on Circuits and Systems最新文献

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Symmetry network and some of their interior properties 对称网络及其一些内部性质
China., 1991 International Conference on Circuits and Systems Pub Date : 1991-06-16 DOI: 10.1109/CICCAS.1991.184295
Zhou Hao, Sun Zhifeng
{"title":"Symmetry network and some of their interior properties","authors":"Zhou Hao, Sun Zhifeng","doi":"10.1109/CICCAS.1991.184295","DOIUrl":"https://doi.org/10.1109/CICCAS.1991.184295","url":null,"abstract":"Some interior properties of symmetry networks are proved by graph theory. It is found that it is convenient to apply them to prove some other network laws.<<ETX>>","PeriodicalId":119051,"journal":{"name":"China., 1991 International Conference on Circuits and Systems","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131558739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
SC parasitic structure conversion with CAD SC寄生结构的CAD转换
China., 1991 International Conference on Circuits and Systems Pub Date : 1991-06-16 DOI: 10.1109/CICCAS.1991.184324
W. Chang, F. Lin, Zheng Li, Yue Lou, Dejun Wang
{"title":"SC parasitic structure conversion with CAD","authors":"W. Chang, F. Lin, Zheng Li, Yue Lou, Dejun Wang","doi":"10.1109/CICCAS.1991.184324","DOIUrl":"https://doi.org/10.1109/CICCAS.1991.184324","url":null,"abstract":"The ability to convert a parasitic structure into a non-parasitic one is of great value in order to achieve systematic design in automatic circuit manufacturing. In this paper, a simple derivation of the biphase switched-capacitor admittance matrix is presented, then an accompanying three-dimensional matrix is provided to help fulfil symbolic operations. In addition, a package to transform a parasitic-sensitive structure to an insensitive one is introduced.<<ETX>>","PeriodicalId":119051,"journal":{"name":"China., 1991 International Conference on Circuits and Systems","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114311402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
ALSAC, an automatic layout system for successive approximation converters 连续逼近转换器的自动布局系统
China., 1991 International Conference on Circuits and Systems Pub Date : 1991-06-16 DOI: 10.1109/CICCAS.1991.184374
A. Yúfera, A. Rueda, J. Huertas, L. París, T. Osés
{"title":"ALSAC, an automatic layout system for successive approximation converters","authors":"A. Yúfera, A. Rueda, J. Huertas, L. París, T. Osés","doi":"10.1109/CICCAS.1991.184374","DOIUrl":"https://doi.org/10.1109/CICCAS.1991.184374","url":null,"abstract":"A new system for the automatic layout of Successive Approximation Charge Redistribution Converters is presented. This system, ALSAC, is able to handle several converter architectures, thus providing designers with a wide flexibility. For all these architectures, ALSAC generates compact layouts preserving matching and symmetry properties, and improving both the area efficiency and performance in comparison with previously reported systems. ALSAC uses a new floorplanning strategy and two module generators. The floorplanning algorithm makes use of slicing structures while considering constraints imposed by the coexistence of analog and digital circuitry in the same IC. The module generators provide the system with very compact realizations of Binary Weighted Capacitor (BWC) and Scaled Switch (SS) Arrays for different specifications and design rules from different foundries.<<ETX>>","PeriodicalId":119051,"journal":{"name":"China., 1991 International Conference on Circuits and Systems","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114366928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A numerical stable algorithm for constructing constrained Delaunay triangulation and application to multichip module layout 构造约束Delaunay三角剖分的数值稳定算法及其在多芯片模块布局中的应用
China., 1991 International Conference on Circuits and Systems Pub Date : 1991-06-16 DOI: 10.1109/CICCAS.1991.184439
Yizhi Lu, W. Dai
{"title":"A numerical stable algorithm for constructing constrained Delaunay triangulation and application to multichip module layout","authors":"Yizhi Lu, W. Dai","doi":"10.1109/CICCAS.1991.184439","DOIUrl":"https://doi.org/10.1109/CICCAS.1991.184439","url":null,"abstract":"Presents some characteristics of constrained Delaunay triangulation and introduces a numerically stable algorithm for incrementally constructing constrained Delaunay triangulation. This algorithm produces constrained Delaunay triangulation at each step. It builds Delaunay triangulation in O(N/sup 2/) time in the worst case. However, its average case performance is O(NlogN). Since the algorithm mainly uses the circle criterion, it arises the precision problem, such as whether a point is inside, outside or exactly on a circle. The authors present a method to conceptually avoid the numerical errors. The experimental results are shown in this paper.<<ETX>>","PeriodicalId":119051,"journal":{"name":"China., 1991 International Conference on Circuits and Systems","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117326327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A method of test generation for large combinational circuits using input vector in pairs 一种使用成对输入向量的大型组合电路的测试生成方法
China., 1991 International Conference on Circuits and Systems Pub Date : 1991-06-16 DOI: 10.1109/CICCAS.1991.184402
Liu Mingjian, Peng Jiehua
{"title":"A method of test generation for large combinational circuits using input vector in pairs","authors":"Liu Mingjian, Peng Jiehua","doi":"10.1109/CICCAS.1991.184402","DOIUrl":"https://doi.org/10.1109/CICCAS.1991.184402","url":null,"abstract":"The authors investigate a new method of test generation for large combinational circuits using input vectors in pairs. The forming rules of the best test codes are derived and analysed. The cut theorem and cut test generation are studied. The experiment results are completely in accordance with the theory. This proves that the test generation approach given the paper is correct and useful.<<ETX>>","PeriodicalId":119051,"journal":{"name":"China., 1991 International Conference on Circuits and Systems","volume":"7 12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116303970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A direct clustering method to analogue circuits fault diagnosis 直接聚类方法在模拟电路故障诊断中的应用
China., 1991 International Conference on Circuits and Systems Pub Date : 1991-06-16 DOI: 10.1109/CICCAS.1991.184405
Zi-chen Hu, Ping Zhong
{"title":"A direct clustering method to analogue circuits fault diagnosis","authors":"Zi-chen Hu, Ping Zhong","doi":"10.1109/CICCAS.1991.184405","DOIUrl":"https://doi.org/10.1109/CICCAS.1991.184405","url":null,"abstract":"This paper presents the direct clustering method in fuzzy clustering diagnosis. This approach can greatly reduce the work of clustering, shorten the time of operation, economize the storage, and so effectively strengthen the capacity of real time operation of fuzzy clustering diagnosis.<<ETX>>","PeriodicalId":119051,"journal":{"name":"China., 1991 International Conference on Circuits and Systems","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123566647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A new neural network model emphasizing importance for associative memory 一种强调联想记忆重要性的新神经网络模型
China., 1991 International Conference on Circuits and Systems Pub Date : 1991-06-16 DOI: 10.1109/CICCAS.1991.184338
D. Yu, Li-Min Yu, Yu-rong Kang
{"title":"A new neural network model emphasizing importance for associative memory","authors":"D. Yu, Li-Min Yu, Yu-rong Kang","doi":"10.1109/CICCAS.1991.184338","DOIUrl":"https://doi.org/10.1109/CICCAS.1991.184338","url":null,"abstract":"The Hopfield network is one of the most important types of neural network, with its readiness for hardware implementation and successful applications in associative memory (AM). However, when used for AM, it has three drawbacks: low capacity, slow convergence speed and weakness. The higher order correlation network (HOCN), suggested by Y.C. Lee (1986), is a direct generalization of the principles which play an important role in the construction of the Hopfield network. It enhances the network's ability by degrees if with a correlation order K (K>2). As for practical applications, unfortunately, difficulties arise due to the complexity in its hardware implementation. In this paper, based on some properties of the human memory, the authors have modified the Hopfield network and suggested a new neural network, emphasizing the importance for AM. It seems the new network has some advantages in its abilities and hardware implementation, so that it is better than both Hopfield's and Y.C. Lee's networks.<<ETX>>","PeriodicalId":119051,"journal":{"name":"China., 1991 International Conference on Circuits and Systems","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130205058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Improved analysis of the nonlinear distortion performance of an N-level analog multiplier 改进了n级模拟乘法器的非线性失真性能分析
China., 1991 International Conference on Circuits and Systems Pub Date : 1991-06-16 DOI: 10.1109/CICCAS.1991.184465
M. T. Abuelma'atti
{"title":"Improved analysis of the nonlinear distortion performance of an N-level analog multiplier","authors":"M. T. Abuelma'atti","doi":"10.1109/CICCAS.1991.184465","DOIUrl":"https://doi.org/10.1109/CICCAS.1991.184465","url":null,"abstract":"The author discusses the nonlinear distortion performance of an N-port analog multiplier under large signal conditions. Analytical expressions are obtained for the output up and down-converted frequencies in terms of the ordinary Bessel functions.<<ETX>>","PeriodicalId":119051,"journal":{"name":"China., 1991 International Conference on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130669185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A BiMOS programmable divider 一个BiMOS可编程分压器
China., 1991 International Conference on Circuits and Systems Pub Date : 1991-06-16 DOI: 10.1109/CICCAS.1991.184473
C. Choy, C. Ho, G. Lunn, B. Lin, G. Fung, R. Chiu
{"title":"A BiMOS programmable divider","authors":"C. Choy, C. Ho, G. Lunn, B. Lin, G. Fung, R. Chiu","doi":"10.1109/CICCAS.1991.184473","DOIUrl":"https://doi.org/10.1109/CICCAS.1991.184473","url":null,"abstract":"The authors describe a BiMOS programmable divider which draws an optimum mix of ECL And CMOS to achieve operating frequency of 165 MHz. Combined with a divide-by-eight prescalar stage, frequencies up to 1.3 GHz can be handled. The programmable divider contains 15 stages of flip-flops configured as a ripple down counter. The first three low order bits are ECL stages and the rest are CMOS stages. Simulation results have suggested that the divider can achieve a division range of 8 to 32767 in steps of unity. Also the reduction of power consumption and the size of the programmable divider are only 35% of a bipolar counterpart.<<ETX>>","PeriodicalId":119051,"journal":{"name":"China., 1991 International Conference on Circuits and Systems","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127859493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Research on LL-DPLL changing order automatically l - dpll自动换序的研究
China., 1991 International Conference on Circuits and Systems Pub Date : 1991-06-16 DOI: 10.1109/CICCAS.1991.184531
Yao Fuqiang, Zhang Juesheng, Du Wulin
{"title":"Research on LL-DPLL changing order automatically","authors":"Yao Fuqiang, Zhang Juesheng, Du Wulin","doi":"10.1109/CICCAS.1991.184531","DOIUrl":"https://doi.org/10.1109/CICCAS.1991.184531","url":null,"abstract":"In order to solve the contradiction between rapid bit-synchronization and filtering the phase noise, a new lead-lag digital phase locked loop (LL-DPLL) is proposed, the design considered and the principle of operation presented in this paper. The theoretical analyses and the experimental results are given also.<<ETX>>","PeriodicalId":119051,"journal":{"name":"China., 1991 International Conference on Circuits and Systems","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126659352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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