{"title":"一个BiMOS可编程分压器","authors":"C. Choy, C. Ho, G. Lunn, B. Lin, G. Fung, R. Chiu","doi":"10.1109/CICCAS.1991.184473","DOIUrl":null,"url":null,"abstract":"The authors describe a BiMOS programmable divider which draws an optimum mix of ECL And CMOS to achieve operating frequency of 165 MHz. Combined with a divide-by-eight prescalar stage, frequencies up to 1.3 GHz can be handled. The programmable divider contains 15 stages of flip-flops configured as a ripple down counter. The first three low order bits are ECL stages and the rest are CMOS stages. Simulation results have suggested that the divider can achieve a division range of 8 to 32767 in steps of unity. Also the reduction of power consumption and the size of the programmable divider are only 35% of a bipolar counterpart.<<ETX>>","PeriodicalId":119051,"journal":{"name":"China., 1991 International Conference on Circuits and Systems","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A BiMOS programmable divider\",\"authors\":\"C. Choy, C. Ho, G. Lunn, B. Lin, G. Fung, R. Chiu\",\"doi\":\"10.1109/CICCAS.1991.184473\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The authors describe a BiMOS programmable divider which draws an optimum mix of ECL And CMOS to achieve operating frequency of 165 MHz. Combined with a divide-by-eight prescalar stage, frequencies up to 1.3 GHz can be handled. The programmable divider contains 15 stages of flip-flops configured as a ripple down counter. The first three low order bits are ECL stages and the rest are CMOS stages. Simulation results have suggested that the divider can achieve a division range of 8 to 32767 in steps of unity. Also the reduction of power consumption and the size of the programmable divider are only 35% of a bipolar counterpart.<<ETX>>\",\"PeriodicalId\":119051,\"journal\":{\"name\":\"China., 1991 International Conference on Circuits and Systems\",\"volume\":\"25 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-06-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"China., 1991 International Conference on Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICCAS.1991.184473\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"China., 1991 International Conference on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICCAS.1991.184473","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The authors describe a BiMOS programmable divider which draws an optimum mix of ECL And CMOS to achieve operating frequency of 165 MHz. Combined with a divide-by-eight prescalar stage, frequencies up to 1.3 GHz can be handled. The programmable divider contains 15 stages of flip-flops configured as a ripple down counter. The first three low order bits are ECL stages and the rest are CMOS stages. Simulation results have suggested that the divider can achieve a division range of 8 to 32767 in steps of unity. Also the reduction of power consumption and the size of the programmable divider are only 35% of a bipolar counterpart.<>
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