A BiMOS programmable divider

Abstract

The authors describe a BiMOS programmable divider which draws an optimum mix of ECL And CMOS to achieve operating frequency of 165 MHz. Combined with a divide-by-eight prescalar stage, frequencies up to 1.3 GHz can be handled. The programmable divider contains 15 stages of flip-flops configured as a ripple down counter. The first three low order bits are ECL stages and the rest are CMOS stages. Simulation results have suggested that the divider can achieve a division range of 8 to 32767 in steps of unity. Also the reduction of power consumption and the size of the programmable divider are only 35% of a bipolar counterpart.<>