{"title":"l - dpll自动换序的研究","authors":"Yao Fuqiang, Zhang Juesheng, Du Wulin","doi":"10.1109/CICCAS.1991.184531","DOIUrl":null,"url":null,"abstract":"In order to solve the contradiction between rapid bit-synchronization and filtering the phase noise, a new lead-lag digital phase locked loop (LL-DPLL) is proposed, the design considered and the principle of operation presented in this paper. The theoretical analyses and the experimental results are given also.<<ETX>>","PeriodicalId":119051,"journal":{"name":"China., 1991 International Conference on Circuits and Systems","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Research on LL-DPLL changing order automatically\",\"authors\":\"Yao Fuqiang, Zhang Juesheng, Du Wulin\",\"doi\":\"10.1109/CICCAS.1991.184531\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In order to solve the contradiction between rapid bit-synchronization and filtering the phase noise, a new lead-lag digital phase locked loop (LL-DPLL) is proposed, the design considered and the principle of operation presented in this paper. The theoretical analyses and the experimental results are given also.<<ETX>>\",\"PeriodicalId\":119051,\"journal\":{\"name\":\"China., 1991 International Conference on Circuits and Systems\",\"volume\":\"9 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-06-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"China., 1991 International Conference on Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICCAS.1991.184531\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"China., 1991 International Conference on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICCAS.1991.184531","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In order to solve the contradiction between rapid bit-synchronization and filtering the phase noise, a new lead-lag digital phase locked loop (LL-DPLL) is proposed, the design considered and the principle of operation presented in this paper. The theoretical analyses and the experimental results are given also.<>
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