Symposium 1988 on VLSI Circuits最新文献_第6页

A technique for real-time measurement of d/sup i/V/dI/sup i/: application to high speed optical communications d/sup i/V/dI/sup i/实时测量技术在高速光通信中的应用

Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037428

R. Swartz

引用次数: 0

A novel BiCMOS TTL input buffer; a merging of analog and digital circuit design techniques 一种新型BiCMOS TTL输入缓冲器模拟和数字电路设计技术的结合

Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037425

H. Tran, P. Fung, D. Scott, R. Havemann, R. Eklund

{"title":"A novel BiCMOS TTL input buffer; a merging of analog and digital circuit design techniques","authors":"H. Tran, P. Fung, D. Scott, R. Havemann, R. Eklund","doi":"10.1109/VLSIC.1988.1037425","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037425","url":null,"abstract":"1 TIL ML The advent of BiCMOS technology brings the availability of bipolar and CMOS components to one silicon chip, and allows the integration oi bipolar high preeirion analog circuita with lower power digital circuitry in next generation of high performance products [l]. This paper will describe a BiCMOS TTL input buffer which employs analog circuit design techniques to enhance the circuit performance. This novel implementation demonstrates the broad range of analog design techniques which can be applied in BiCMOS digital c k u i t s . The Mynchronoua operation CMOS TTL input buffer has two major obstacles that have been taunting IC circuit designers-for years. First is the variations of input trip point across power .up ply, process and temperature. Second is the high power dissipation of the buffer's first stage inverter, which results from the small voltage swing of the TTL input level. Furthermore, for eompatibility to the standby power requirements of the existing products, a CMOS input buffer often must be gated by an enabling signal for switching lo and from the standby mode. These problems require compromises to be made between speed, power, yield and reliability. and thus tend to degrade the overall performance oi the device. The transistor i i a e s of the buffer's fint stsge inverter are chosen surh that the DC trip point is centered et a midpoint of the TTL input level (1.4 volts). However, as process, power supply and temperature fluctuate. the DC trip point deviates away from the midpoint and reduces the input signal margins, as shown in figure 1. In additional, a significant current is Bowing in the CMOS input buffer when its input 1s at TTL VIH level of 2.0 volts, M shown in figure 2a. This current is caused by the CMOS input buffer's first stage inverter which is partially in an on state. reference voltage of 1.4 volts LO II Threshold Reference (TREF) ckcuit to establish a CMOS inverter trip point dependent VTH signal. This signal is connected to bipolar transistor Q1 to supply a rcgulated voltage level to the source of the Pchannel pull-up MP1. This voltage level is designed to keep the trip point of the TCON input buffer's h t stage inverter at the midpoint of TTL high and low levels. The transistor sizes of the first stage inverter M also chosen such that the voltage a t the source ofthe Pchannel MPI ir alwayat or below L voltage level of (VTTLhi + Vtp); where VTTLhi is the TTL logic high level of 2.0 volts and Vtp is the Vt of the Pchanne1 transistor. Figure 2b shows a plot of the current of the TCON input buffer vs its input voltage when condition stated above is satisfied. The buffer (current is essentially ~ e r o when its input is held at a valid TTL level. This important feature allows the standby to active enabling signal to he omitted from the design of the input circuitry. The elimination of this enabling signal allows faster eircui1 operation because the output of the buffer is in II correct logic state during the ","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127253593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A circuit design of 32Kbyte integrated cache memory 一种32Kbyte集成高速缓存的电路设计

Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037416

T. Sakurai, K. Nogami, K. Sawada, T. Shirotori, T. Takayanagi, T. Iizuka, T. Maeda, J. Matsunaga, H. Fuji, K. Maegucm, K. Kobayasm, T. Ando, Y. Hayakasfh, T. Mfyosfu, K. Sato

引用次数: 11

A compilable binary tree parallel multiplier designed for speed and testability 一个可编译的二叉树并行乘法器设计的速度和可测试性

Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037439

G. Venzl, R. Mitchell

引用次数: 1

A 6.2 ns 64Kb CMOS RAM with ECL interfaces 具有ECL接口的6.2 ns 64Kb CMOS RAM

Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037404

T. Chappell, S. Schuster, B. Chappell, J. Allan, S. Klepner, R. Franch, P. Greier, P. Restle

引用次数: 10

A 6.75ns single level metal CMOS 16x16 multiplier IC 6.75ns单电平金属CMOS 16x16乘法器IC

Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037438

R. Shamz, A. Lopez, J. Michejda, S. Hillenius, J. M. Andrews, A. J. Studwell

引用次数: 4

Realization of FIR and IIR ftlters using SC differentiators 用SC微分器实现FIR和IIR滤波器

Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037442

Chung-Yu Wu, Tsai-Chung Yu, Shin-Chih Chang

引用次数: 1

A 1/2 inch-CCD imager with low-voltage variable shutter 1/2英寸ccd成像仪，低压可变快门

Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037454

H. Ando, M. Naxai, H. Ono, N. Ozawa, S. Ouba, T. Suzuki, M. Ufuara, I. Taxemoto

引用次数: 1

A 5.5 MIPS call handling processor for switching systems 用于交换系统的5.5 MIPS呼叫处理处理器

Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037412

T. Morita, T. Hayashi, Y. Saita, T. Ohno, S. Yoshida, T. Fukuda, R. Ikeda

引用次数: 1

A 14ns 256K CMOS SRAM with internal parity 带有内部奇偶校验的14ns 256K CMOS SRAM

Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037415

T. Seki, E. Ito, K. Komatsu, T. Yabu, N. Suzuki

引用次数: 0