Symposium 1988 on VLSI Circuits最新文献_第5页

A 256K CMOS EEPROM with enhanced reliability and testability 256K CMOS EEPROM，增强了可靠性和可测试性

Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037434

J. Do, J. K. Kim, H. G. Lee, J. Choi, H. Lim

{"title":"A 256K CMOS EEPROM with enhanced reliability and testability","authors":"J. Do, J. K. Kim, H. G. Lee, J. Choi, H. Lim","doi":"10.1109/VLSIC.1988.1037434","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037434","url":null,"abstract":"This paper will describe a 32K x 8 CMOS EEPROM with on-chip ECC (Error Checking and Correction). Test features that enable effective testing of the on-chip ECC circuit and cell thrshold voltage will be described. A novel electrically programmable fuse circuit renders reliable implementation of redundancy and programmable optional features. The 5V full-featured [ I ] , [2] EEPROM with 64-byte page write mode has additional test features such as ECC disable, write cycle and program voltage (Vpp) ramp speed control, and write inhibit Vcc level adjustment. A double-poly, single-metal N-well CMOS technilagy with thin tunnel-oxide ( < I O O A O ) floating-gate cell is used to build the EEPROM. Minimum feature size 1 . 2 um is used to achieve 60 um' cell size and 68 mm' chip size. A 350A' composite interpoly dielectric is used to provide enhanced cell data retention characteristics. Far high voltage path, graded junction formed by double ion implantation is used to increase breakdown voltage. A modified Hamming code ECC scheme, having 4 parity cells per byte, is implemented with extended test features (Figure 1). Since most of endurance and data retention failures in a thin-oxide floating-gate EEPROM are caused by random defects in tunnel oxide, which can be corrected by the ECC scheme if not multiple in a byte, reliability of the EEPROM is drastically improved by the ECC scheme when the chip is properly tested. Parity code generator, core array data bits, and core array parity bits can be tested in separated modes. This separated testing is essential to production of highly reliable EEPROM and to direct evaluation of ECC impact an the chip reliability and yield. In the parity code check mode ( H 1 high), the parity generator is tested in a read speed by forming a closedloop circuit consisted of data-in buffer, parity code generator, and data-out buffer, as shown in dash lines in Figure 1. In this mode, when OE is low, input data is latched at the data-in buffer and corresponding parity code can be read from the data-out buffer. In the ECC disable made (H3 high), core array data bits are checked without correction, whereas core array parity bits are tested in the parity bit check mode (H2 high). Threshold voltage of each cell in the core array, used for precise monitoring of charge retention characteristic, is measured by excecuting a read cycle with external voltage applied to the cell control-gate line (Figure 2 ) . The external voltage is applied through pass transistors, the gates of which are connected to output of a high voltage follower circuit shown in Figure 3. Since the output of the high voltage follower circuit is grounded when input voltage is lower than the trip voltage, which is always about 3 Vt above Vcc, this threshold measurement scheme does not affect normal operation. In the threshold measurement mode, however, external voltage higher than Vcc can be transfer to the control-gate line by applying high voltage to the input of the foll","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132169167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

GHz band high gain GaAs monolithic amplifiers using parallel feedback technique 采用并行反馈技术的GHz频段高增益GaAs单片放大器

Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037400

N. Ishihara, H. Kikuchi, M. Ohara

引用次数: 1

8ns 64K BiCMOS SRAM's 8ns 64K BiCMOS SRAM

Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037405

H. Miwa, K. Tsuruoka, K. Yamauchi, H. Endoh, M. Odaka, Y. Saito

引用次数: 0

A 1024-channel time switch LSI with an operating frequency of 50MHz 一个工作频率为50MHz的1024通道时间开关LSI

Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037447

K. Aoyama, K. Narita, S. Karafuji, K. Nagai, K. Matsumoto

引用次数: 2

Bipolar scaling for BiCMOS circuits BiCMOS电路的双极标度

Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037426

G. P. Rosseel, R. Dutton

引用次数: 5

New DRAM noise generation under half Vcc precharge and its reduction using a transposed amplifier 半Vcc预充条件下的新型DRAM噪声产生及其用转置放大器的降低

Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037432

S. Ienaga, M. Aoki, Y. Nakagome, M. Horiguchi, Y. Kawase, Y. Kawamoto, K. Itoh

引用次数: 7

A programmable SLIC consisting of both SCF and DSP technologies with 30dB return loss characteristics 具有30dB回波损耗特性的可编程SLIC，由SCF和DSP技术组成

Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037446

T. Okamoto, J. Hirakawa, S. Morisaki, Y. Kurose, M. Takeda, K. Shiraki

引用次数: 0

Neural networks and expectation of VLSI implementation 神经网络和VLSI实现的期望

Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037406

M. Kawato, S. Miyake, T. Inui

{"title":"Neural networks and expectation of VLSI implementation","authors":"M. Kawato, S. Miyake, T. Inui","doi":"10.1109/VLSIC.1988.1037406","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037406","url":null,"abstract":"2.1 Transformation Neural Network Computational neuroscience and its application to The most fundamental motivation for exploring neuengineering “neurocomputing” have been a subject ral networks as a guide to future information processof great interest for the past several years. Research ing machines comes from the fact that we do have of neurocomputing is expected to lead to developits most fascinating realization as the human brain. ment of massively parallel network systems based Neural networks have at least two remarkable charon neural network models: neurocompufer. There acteristics in contrast with the present von Neumann seems to be several reasons for the recent resurgence type computer. First it h a s the capability of learning of interest in neural network as an information prowith use of plastic changes of synaptic connections cessing machine. (i) Improvement of computer fabetween its computing elements neurons. Second it cility as a tool for simulating neural network modsolves computational problems by cooperative operels. (ii) Increasing feasibility of hardware implemenation of great number of neurons (10” in-the brain). tation of neural network models by analogue VLSI [1,2,3], optoelectronic devices [4] etc. (iii) Steady deAccording to the above two features, many Of the velopment of experimental neuroscience. (iV) connetwork models, which were proposed t o account for sidetable amount of fundamental principles and neubrain functions such pattern recognition or memral network models accumulated during past 25 years ory in a somewhat abstract can be classiresearch of biological information processing. (v) AI fied into the two The research, which aims at the similar intelligence as huis called as “transformation” neural network model","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125214993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A new nibbled-page architecture for high density DRAMs 一种用于高密度dram的新型咬页架构

Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037429

K. Numata, Y. Oowaki, Y. Itah, T. Hara, H. Tsuchida, T. Kobavashi, M. Ohta, S. Watanabe, K. Ohuchi

引用次数: 1

A CMOS nondifferential static sampling sense amplifier 一种CMOS非差分静态采样感测放大器

Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037449

V. Pinto, R. Marko, E. Cohen, J. Levy, L. Lev

引用次数: 0