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A new CR-delay circuit technology for high-density and high-speed DRAMs 一种用于高密度高速dram的cr延迟电路新技术
Symposium 1988 on VLSI Circuits Pub Date : 1989-08-01 DOI: 10.1109/VLSIC.1988.1037430
Y. Watanabe, T. Ohsawa, K. Sakurai, T. Furuyama
{"title":"A new CR-delay circuit technology for high-density and high-speed DRAMs","authors":"Y. Watanabe, T. Ohsawa, K. Sakurai, T. Furuyama","doi":"10.1109/VLSIC.1988.1037430","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037430","url":null,"abstract":"The capacitance-resistance (CR) delay circuit technology assures full asynchronicity between memory cell array and peripheral circuits over a wide range of both operating and process conditions and thus realizes a fast access time. A noise compensation scheme is used to generate a constant delay even under the power supply line noise. The circuit was applied to a 4 Mbit dynamic RAM (DRAM) peripheral circuit. As a result, timing loss as well as malfunction could be successfully avoided, and 7 ns faster access time and 39 ns shorter cycle time, compared with a conventional design using normal inverter chains, have been achieved. >","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121233280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Using active components to perform voltage division in digital-to-analog conversion 在数模转换中使用有源元件进行分压
Symposium 1988 on VLSI Circuits Pub Date : 1989-08-01 DOI: 10.1109/VLSIC.1988.1037452
C. P. Chong, K. C. Smith, Z. Vranesic
{"title":"Using active components to perform voltage division in digital-to-analog conversion","authors":"C. P. Chong, K. C. Smith, Z. Vranesic","doi":"10.1109/VLSIC.1988.1037452","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037452","url":null,"abstract":"The design of a voltage-mode digital-to-analog (D/A) converter using only fabrication steps required by MOSFETs is described. The converter is implemented using a basic-circuit-building block called the three-input amplifier (TIAMP), which can perform voltage addition and voltage division by 2 without using any passive component. The technique has been used to implement a 12 bit D/A converter for which five samples were tested with accuracies ranging from 6 to 10 bits. Accuracy is limited in the present design by the relatively small sizes chosen for the input transistors. The maximum conversion rate of the present prototypes has been measured to be approximately 1 MHz with a static power dissipation of 50 mW. >","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125688084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 50 dB variable gain amplifier using parasitic bipolar transistors in CMOS 采用CMOS寄生双极晶体管的50db可变增益放大器
Symposium 1988 on VLSI Circuits Pub Date : 1989-08-01 DOI: 10.1109/VLSIC.1988.1037399
T. Pan, A. Abidi
{"title":"A 50 dB variable gain amplifier using parasitic bipolar transistors in CMOS","authors":"T. Pan, A. Abidi","doi":"10.1109/VLSIC.1988.1037399","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037399","url":null,"abstract":"A variable-gain amplifier (VGA) with a gain range of 50 dB has been implemented in a standard 3 mu m CMOS process using parasitic lateral and vertical bipolar transistors to form the core of the circuit. The bipolar transistors had been characterized extensively. The VGA has a bandwidth larger than 3 MHz over the whole gain range and operates on a single 5 V power supply. The active area is about 0.8*0.9 mm/sup 2/. >","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130515919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 96
Design of a 32bit microprocessor, TX1 32位微处理器TX1的设计
Symposium 1988 on VLSI Circuits Pub Date : 1988-12-01 DOI: 10.1109/VLSIC.1988.1037410
T. Tokwnaru, E. Masada, C. Hori, K. Usami, M. Miyata, J. Iwamura
{"title":"Design of a 32bit microprocessor, TX1","authors":"T. Tokwnaru, E. Masada, C. Hori, K. Usami, M. Miyata, J. Iwamura","doi":"10.1109/VLSIC.1988.1037410","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037410","url":null,"abstract":"","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132010977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A single-chip adaptive DPCM intrafield video codec 单片自适应DPCM场内视频编解码器
Symposium 1988 on VLSI Circuits Pub Date : 1988-09-01 DOI: 10.1109/VLSIC.1988.1037444
M. Schdbinger, B. Zehner, F. Matthiesen, U. Totzek, J. Hartl, U. Reimann, R. Tielert
{"title":"A single-chip adaptive DPCM intrafield video codec","authors":"M. Schdbinger, B. Zehner, F. Matthiesen, U. Totzek, J. Hartl, U. Reimann, R. Tielert","doi":"10.1109/VLSIC.1988.1037444","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037444","url":null,"abstract":"A DPCM video codec for two-dimensional prediction with adaptive quantizer is presented. The necessary line buffer is realized on chip. Transmitter or receiver mode, application as part of a 3D interframe codec, and processing of luminance or chrominance signals are optional. Correct operation has been verified up to 26 MHz.","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115675372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 14ns 256kx1 CMOS SRAM with multiple test modes 具有多种测试模式的14ns 256kx1 CMOS SRAM
Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037414
L. Pfermings, C. Phelan, P. Voss, T. Davies, C. O'Connell, S. Bell, R. Salters, H. Ontrop
{"title":"A 14ns 256kx1 CMOS SRAM with multiple test modes","authors":"L. Pfermings, C. Phelan, P. Voss, T. Davies, C. O'Connell, S. Bell, R. Salters, H. Ontrop","doi":"10.1109/VLSIC.1988.1037414","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037414","url":null,"abstract":"The memory organization is partitioned into four 64k matrices. The power to the submicron CMOS memory cells is supplied by an on-chip switching voltage regulator. The 3.9V matrix supply protects the memory cells against hot carrier stress and ensures high cell noise margins'. In the 5V periphery, 1 . 3 ~ NMOS cascode devices were integrated'. Each matrix is organized in 128 rows by 512 columns and is further divided into 16 blocks of 32 columns, utilizing a divided word line structure3. A common read/write block area with local sense amplifiers and write drivers is shared between each pair of matrices. A matrix global Y-select signal enables one of eight columns and precharges the remaining unselected columns to the matrix voltage (VDI).","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"275 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115113566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 17-bit over-sampling D/A conversion technology using multi-stage noise shaping 采用多级噪声整形的17位过采样D/A转换技术
Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037451
Y. Matsuya, K. Uchimura, A. Iwata
{"title":"A 17-bit over-sampling D/A conversion technology using multi-stage noise shaping","authors":"Y. Matsuya, K. Uchimura, A. Iwata","doi":"10.1109/VLSIC.1988.1037451","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037451","url":null,"abstract":"","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115155797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 4Gb/s GaAs 16-1multiplexer/1-16demultiplexer LSI 4Gb/s GaAs 16-1多路复用/1-16解路复用LSI
Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037436
M. Ida, T. Takada, N. Kato
{"title":"A 4Gb/s GaAs 16-1multiplexer/1-16demultiplexer LSI","authors":"M. Ida, T. Takada, N. Kato","doi":"10.1109/VLSIC.1988.1037436","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037436","url":null,"abstract":"","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124435047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An experimental Bi-CMOS video 10bit ADC 一个实验性的双cmos视频10位ADC
Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037457
Y. Sugimoto, S. Mizoguchi
{"title":"An experimental Bi-CMOS video 10bit ADC","authors":"Y. Sugimoto, S. Mizoguchi","doi":"10.1109/VLSIC.1988.1037457","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037457","url":null,"abstract":"","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124998923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A CMOS operational amplifier with load- and signal-independent settling time 具有负载和信号无关的稳定时间的CMOS运算放大器
Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037398
R. Klinke, B. Hosticka, H. Pfleiderer, G. Zimmer
{"title":"A CMOS operational amplifier with load- and signal-independent settling time","authors":"R. Klinke, B. Hosticka, H. Pfleiderer, G. Zimmer","doi":"10.1109/VLSIC.1988.1037398","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037398","url":null,"abstract":"","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125422314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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