Symposium 1988 on VLSI Circuits最新文献_第2页

Pipelined parallel bidirectional shift (PPB) architecture for high speed serial access 用于高速串行访问的流水线并行双向移位(PPB)架构

Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037437

Y. Norooka, T. Kobayashi, K. Yasuda, M. Yanada

引用次数: 0

A new pipelined-subranging 8 bit 20MHz CMOS AD converter 一种新型流水线分程8位20MHz CMOS模数转换器

Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037456

K. Tsuji, S. Saitoh, S. Morinaga, T. Iida

引用次数: 4

Improvement of soft error rate in MOS SRAMs MOS固态存储器软错误率的改进

Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037422

S. Murakami, K. Ichinose, K. Anami, S. Kayano

引用次数: 2

1.5um CMOS gate arrays with analog/digital macros designed using the common base arrays 采用通用基阵设计的带模拟/数字宏的1.5um CMOS门阵列

Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037424

S. Kawada, Y. Hara, T. Isono, T. Inuzuka

{"title":"1.5um CMOS gate arrays with analog/digital macros designed using the common base arrays","authors":"S. Kawada, Y. Hara, T. Isono, T. Inuzuka","doi":"10.1109/VLSIC.1988.1037424","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037424","url":null,"abstract":"Mixed analog and digital circuits are realized on a single chip of 1.5um rule, single t5V power supplied, si.licon gate, and 320 through 19600 cells CMOS digital gate arrays without any extension of turn-around time and any restriction of designing. Voltage comparator with input offset voltage of lOmV MAX. and response time of 60nsec. D/A converters and A/D converters with 4 bit, 6 bit, 8 bit respectively, and an analog switch with 250hm on-resistance can exist simultaneously with digital circuits. Using this technology, about 1/10 of turnaround time on system developments compared with full-custom LSIs can be achieved. INTRODUCTION I t is desired eagerly in the semi-custom LSI field to integrate a system on a single chip by establishing a mixture of analog and digital technologies. Up to this time, there are a few ways to create mixed analog and digital circuits; i.e., full-custom LSIs, standard cells, masterslice LSIs which have more than 2 channel length transistors for analog circuit parts and digital circuit parts. or gate array of which all base transistor arrays are long channel length type [ I ] , t21. Each of them have several weak points, for example long turn-around time, high development Cost, restriction of the ratio between analog circuit parts and digital circuit parts, very Poor digital circuit's performance, and so on. STRUCTURES Analog function blocks are produced on base transistor arrays of commonly used 1.5um rule, single +5V power.supplied, and silicon gate CMOS digital gate array series. This gate array series contains 16 masters with 320 through 19600 cells. Figure 1 shows a microphotograph of a chip including analog function blocks. All of analog circuits can be placed anywhere on the base transistor arrays with only a few consideration (ex. cross talk. noise etc.) like digital circuits. These analog function blocks are registered as hardware macros in function block libraries. PRODUCTS DEVELOPMENT FLOW Gate arrays including analog circuits are developed according to the flow chart shown in Figure 2 . Just the same development flow and CAD tools of designing gate arrays with only digital circuits are used. In case of circuit simulation, analog function blocks are treated as black boxes. And only connections between analog function blocks and other blocks are checked. In this way, the turn-around time from the end o f the circuit simulation to the supply of engineering sample of mixed analog and digital circuits is reduced to about 1/10 compared with fullcustom LSIs. VOLTAGE COUPARAT ORS short channel length unit transistors such as: Wp/Lp = 33um/1.8um All analog circuits are constructed with WN/LN = 33um/1.6um, Figure 3 shows one of the comparator's layout pattern. Input transistors of differential Stage uses two unit transistors each, and they are placed cross coupled with each other. And power supply wires are also placed equally for the input pair transistors. The comparator's layout is made under such consideration, a","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128912582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Fast converging analog adaptive filter for general purpose noise canceller 用于通用降噪的快速收敛模拟自适应滤波器

Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037441

T. Ritoniemi, T. Karema, H. Tenhunen

引用次数: 4

16Mb ROM design using bank select architecture 使用银行选择架构的16Mb ROM设计

Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037435

M. Okada, Y. Hotta, R. Matsuyama, Y. Surninaga, J. Tanimoto, K. Nakahara, M. Takahi, H. Korniya, T. Ashida, K. Sane, A. Kunikane, R. Miyake

引用次数: 7

High-density quaternary logic array chip for knowledge information processing systeks 用于知识信息处理系统的高密度四元逻辑阵列芯片

Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037408

T. Hanyu, T. Higuchi

{"title":"High-density quaternary logic array chip for knowledge information processing systeks","authors":"T. Hanyu, T. Higuchi","doi":"10.1109/VLSIC.1988.1037408","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037408","url":null,"abstract":"instance, production systemshave been observed to spend more than nine-tenths of its total run time performing the pattern matching. The knowledge information processing system requires high computational power and large memory capacity at low cost to make many kinds of real-time applications possible [ 1 I . This paper presents a new high-density quaternary logic array chip for high-speed pattern matching instead of depending on expensive and time-consuming software systems 121. A double pattern matching algorithm can be effectively employed for achieving greater densities on smaller semiconductor chips. The appropriate quaternary encoding for the contents of B working memory and a production memory can perform a double pattern matching. Four states for two-bit information concerning with two elements of a rule can be stored into a pattern matching cell using multiple ion implant technique which makes the threshold of the transistor programmable [ 3 ] , A9 a result, the pattern matching cell can be implemented by using only a single transistor. The number. of cells and transistors in the proposed logic array are reduced to 50% of the corresponding binary implementation. Moreover, the pattern matching operations can be performed in parallel, so that the processing time on each reasoning cycle can be provided by the propagation delay time of a single transistor. information processing system interpreters. For","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116152289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A multiplying encoder for digital signal processing 用于数字信号处理的乘法编码器

Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037443

K. Okada, S. Takeuchi, M. Kimura, T. Kumamoto, N. Yazawa

引用次数: 1

A 0.1/spl mu/A standby current, bouncing-noise-immune 1Mb SRAM 一个0.1/spl mu/A待机电流，抗弹跳噪声1Mb SRAM

Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037418

M. Ando, T. Okazawa, H. Furuta, M. Ohkaaa, J. Monden, N. Kodama, K. Are, H. Ishihara, I. Sasaki

引用次数: 16

Mixed-mode simulation and verification: status and future 混合模式仿真与验证:现状与未来

Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037423

D. Smith

引用次数: 0