Symposium 1988 on VLSI Circuits最新文献_第3页

A 0.5 GHz BiCMOS operational amplifier 一种0.5 GHz BiCMOS运算放大器

Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037397

M. Nayebi, B. Wooley

引用次数: 1

VLSI chip-set for personal computers 用于个人计算机的VLSI芯片组

Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037411

T. Machida, T. Matsuda, F. Tsukuda, R. Hashishita

{"title":"VLSI chip-set for personal computers","authors":"T. Machida, T. Matsuda, F. Tsukuda, R. Hashishita","doi":"10.1109/VLSIC.1988.1037411","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037411","url":null,"abstract":"This paper will describe a V U 1 chip-set for Personal Computers. It consists of Peripheral Controller (PERIJ made of I1 standard peripheral mega-macro block, Text Controller (CRZT), and Graphics Controller (CRTG). The chips fully utilize hierarchical automatic layout design system. 205K transistors have been integrated by a three chip-set. They have been fabricated by I.5pm double metal-layer CMOS process technology. The chip-set allows to design a personal computer of M-size with CPU, memory and some inteqace logics. The personal computer consumes only 114 of power. compared to a standard version with the same system configuration. Introduction : This paper describes a VLSI chip-set for Personal Computers. The set consists of Peripheral Controller (PERI), Text Controller (CRm), and Graphics Controller bus and address bus. Bus controller gives bus interface Control signals, such as memory readlwrite and I10 readwrite, to mega-macro blocks. Custom-macro blocks are provided to realize user-defined functions, such as timing control of the device, extemal interface, offchip memory interface, and so on. Standard cell approach realizes these custom-macros. Microphotograph of the chip is shown in Fig.3. The CRTT contains a Graphic Display Controller (GDC) mega-macro and 5.4K-gate custom-macro.The CRTG contains a GDC and 11 .5K-gate custom-macro. Table 1 summarizes features of three chips. Fig.4 shows an example of PC system configuration by the chip-set. As is shown, only the interface logics are required, in addition to ROM/RAM and CPU. Mega-Macro Blocks : The mega-macro blocks are the (CKIti). A VLSI chip-set which integrates various standard peripheral LSIs is highly required by system vendors so that a small system with low Power consumption can be realized. In this case, the chip-set should be software-compatible with the off-the-shelf standard peripheral LSIs, and should be developedin shortperiod. A simple way of implementing such VLSIs without modifying the original LSIS tends to have enormous chip area. Entirely new design of standard LSI by another technology, such as standard cell approach, also has enormous man-power to modify existing standard LSI circuit for standard cell. mozified versions of standard m&roprocessor peripheral controllers. Features of mega-macros are shown in Table 2. Use of a mega-macro block reduces the number of transistors and area size, compared to the standard cell approach. For example, the PI0 mega-macro block has 2,500 transistors, however it would have 4,400 transistors if it were designed by using standard cell technique. In the PERI-chip case, this technique has reduced 37% of total chip size than the standard cell design. The original layout of standard LSIs were used as first approximation of mega-macro blocks, then VO pads were stripped out to have the smallest block area. It has brought 25% to 54% of area reduction, compared to ones with The chip-set has been developed to fulfill these I/O Dads. The oumut ","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121738748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Enhanced implication for automatic test pattern generation 增强了自动测试模式生成的含义

Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037427

S. Hamilton

引用次数: 0

Network-component chip set for a parallel processor system 用于并行处理器系统的网络组件芯片组

Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037413

K. Kaneko, S. Goldta, T. Kishi, Y. Tsue, K. Zaiki, M. Watanabe, T. Mimura, H. Kadota

{"title":"Network-component chip set for a parallel processor system","authors":"K. Kaneko, S. Goldta, T. Kishi, Y. Tsue, K. Zaiki, M. Watanabe, T. Mimura, H. Kadota","doi":"10.1109/VLSIC.1988.1037413","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037413","url":null,"abstract":"Introduction For the past twenty years. parallel processing has been considered a promlslng technlque for hlgh-performance computers of the next generation. Recently. several machlnes wlth parallel architecture have become commercially available. but their performancc Is lower than what has been expected. One of the maJor problems to be solved for a hlgh performancc parallel machlne Is deslgnlng a n efficlent network for transfenlng data between the processor elements (PES). A new network Structure for a parallel processor system. ADENA. has been proposed[ll. which wlll reallze emdent data transmlsslon and hlgh-speed numerical computatlon. In thls paper. two component devlces. a chlp set for bulldlng that network, wlll be descrlhed. The first chip. HM. Is a high-performance bldlrectional Buffer-Memory (FIFO) array. and the second chlp. SRC. Is a data-Send/ReecRc Controller. Two new techniques are used to get a hlgh data-hansfa rate: 11 Metchlng Butfn-Memory status I : empty/rUll I by SRC. 21 C m l t deslgn for a high-speed RFO wlth m m u m readnow-hugh ume. The peak data-transfer rate through these chips is zOMBytes/s for each bus. The structure and the usage of the network are also dlscussed.","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131557983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Memory design strategy 内存设计策略

Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037402

S. Matsue

引用次数: 0

A 7.5ns 32K x 8 high-speed CMOS SRAM 7.5ns 32K x 8高速CMOS SRAM

Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037417

H. Okuyana, T. Nakano, S. Nishida, Jun Fukuchi, S. Arita

{"title":"A 7.5ns 32K x 8 high-speed CMOS SRAM","authors":"H. Okuyana, T. Nakano, S. Nishida, Jun Fukuchi, S. Arita","doi":"10.1109/VLSIC.1988.1037417","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037417","url":null,"abstract":"11. CIRCUIT CONFIGURATION The chip architecture of the RM is shown in Figure 1. The memry cell array is divided into 32 blocks allovs divided-word-line architecture. A main vord line runs Y-direction in the second-level metal and the divided vord lines drives only 64 memory cells. A bit line, vhich runs X-direction in the first-level =tal. is connected to only 128 memory cells. Also. only one of 32 blocks is activated remining other blocks in a standby state so that the pover dissipation is reduced. Figurq 2 and 3 shov the read out circuit and the internal timing diagram of theRAN. Double Activated Pulse: Yo&Line-Enable(nE) pulse and SenseAmplifier-Enable&#) pulse are generated by the Ampulse vhich is generated by detecting the transition of all addresses and CE input. So far the WLEpulse. vhich activates the vord line. was generated by the fallins edge of the ATl-pulse to obtain immunity against address skevs. This technique hinders the high speed access because of its stable operation. But in this RAN the LE-pulse is generated by the rising e k e of the ATl-pulse. not by the falling edge, so that the vord line is immediately turned on after an address transition occurs. Therefore it has been possible to reduce access time by the active period o f the ATD-pulse. On the other hand in order to o h i n sufficient immunity against address skevs. the SAE-pulse vhich activates the bus lines and the sense amplifiers is generated by the falling e k e of the ATl-pulse. The RC delay both of the rord lines and of the bit lines are reduced by the chip architecture. \"he bus lines and the sense amplifiers are activated after all address changes have been stable. Consesuentlv it has been possible to obtain immunity aminst address skevs. After the data is E c h e d to the output buffer, the =-pulse and the SAE-pulse are inactivated . (1) Therefore, the power dissipation has been reduced in case of a long cycle read operation. Consequently. the high speed access, the lor pover dissipation and the complete immunity against address skevs have been achieved by usim this Double Activated Pulse circuit. To reduce the transition time of the output buffer, nev data output reset circuit has been developed. The data output is reset to a intermediate level before the true data output appars. In this circuit, the current through both the data output nchannel and p-channel HOSFET's is nothing. The true data output changes from the intermediate level. Therefore it has been possible to achieve the high speed access and to diminish the noise vhich occurrs oving to the peak current of the output buffer.","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131798581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

The TRON project and development of a TRON-spec 32-bit microprocessor TRON项目和TRON规格32位微处理器的开发

Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037396

K. Sakamura, K. Kimbara, Y. Tominaga

引用次数: 0

RSD cyclic analog-to-digital converter RSD循环模数转换器

Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037455

B. Ginetti, A. Vandemeulebroecke, P. Jespers

引用次数: 17

A high-performance VFO-LSIusing 2-/spl mu/m CMOS analog and digital standard cell methodology 采用2-/spl μ m CMOS模拟和数字标准单元方法的高性能vfo - lsiv

Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037450

S. Fujii, H. Satoh, H. Shimizu, K. Matsuo, M. Kaizuka, I. Tsuchiya, K. Kasai

引用次数: 1

A video frequency bit-parallel CMOS FIR median hybrid filter 一种视频位并行CMOS FIR中值混合滤波器

Symposium 1988 on VLSI Circuits Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037445

O. Vainio, H. Tenhunen, T. Korpiharju, J. Tomberg, Y. Neuvo

引用次数: 4