Network-component chip set for a parallel processor system

Abstract

Introduction For the past twenty years. parallel processing has been considered a promlslng technlque for hlgh-performance computers of the next generation. Recently. several machlnes wlth parallel architecture have become commercially available. but their performancc Is lower than what has been expected. One of the maJor problems to be solved for a hlgh performancc parallel machlne Is deslgnlng a n efficlent network for transfenlng data between the processor elements (PES). A new network Structure for a parallel processor system. ADENA. has been proposed[ll. which wlll reallze emdent data transmlsslon and hlgh-speed numerical computatlon. In thls paper. two component devlces. a chlp set for bulldlng that network, wlll be descrlhed. The first chip. HM. Is a high-performance bldlrectional Buffer-Memory (FIFO) array. and the second chlp. SRC. Is a data-Send/ReecRc Controller. Two new techniques are used to get a hlgh data-hansfa rate: 11 Metchlng Butfn-Memory status I : empty/rUll I by SRC. 21 C m l t deslgn for a high-speed RFO wlth m m u m readnow-hugh ume. The peak data-transfer rate through these chips is zOMBytes/s for each bus. The structure and the usage of the network are also dlscussed.