A 7.5ns 32K x 8 high-speed CMOS SRAM

11. CIRCUIT CONFIGURATION The chip architecture of the RM is shown in Figure 1. The memry cell array is divided into 32 blocks allovs divided-word-line architecture. A main vord line runs Y-direction in the second-level metal and the divided vord lines drives only 64 memory cells. A bit line, vhich runs X-direction in the first-level =tal. is connected to only 128 memory cells. Also. only one of 32 blocks is activated remining other blocks in a standby state so that the pover dissipation is reduced. Figurq 2 and 3 shov the read out circuit and the internal timing diagram of theRAN. Double Activated Pulse: Yo&Line-Enable(nE) pulse and SenseAmplifier-Enable&#) pulse are generated by the Ampulse vhich is generated by detecting the transition of all addresses and CE input. So far the WLEpulse. vhich activates the vord line. was generated by the fallins edge of the ATl-pulse to obtain immunity against address skevs. This technique hinders the high speed access because of its stable operation. But in this RAN the LE-pulse is generated by the rising e k e of the ATl-pulse. not by the falling edge, so that the vord line is immediately turned on after an address transition occurs. Therefore it has been possible to reduce access time by the active period o f the ATD-pulse. On the other hand in order to o h i n sufficient immunity against address skevs. the SAE-pulse vhich activates the bus lines and the sense amplifiers is generated by the falling e k e of the ATl-pulse. The RC delay both of the rord lines and of the bit lines are reduced by the chip architecture. "he bus lines and the sense amplifiers are activated after all address changes have been stable. Consesuentlv it has been possible to obtain immunity aminst address skevs. After the data is E c h e d to the output buffer, the =-pulse and the SAE-pulse are inactivated . (1) Therefore, the power dissipation has been reduced in case of a long cycle read operation. Consequently. the high speed access, the lor pover dissipation and the complete immunity against address skevs have been achieved by usim this Double Activated Pulse circuit. To reduce the transition time of the output buffer, nev data output reset circuit has been developed. The data output is reset to a intermediate level before the true data output appars. In this circuit, the current through both the data output nchannel and p-channel HOSFET's is nothing. The true data output changes from the intermediate level. Therefore it has been possible to achieve the high speed access and to diminish the noise vhich occurrs oving to the peak current of the output buffer.