High-density quaternary logic array chip for knowledge information processing systeks

Abstract

instance, production systemshave been observed to spend more than nine-tenths of its total run time performing the pattern matching. The knowledge information processing system requires high computational power and large memory capacity at low cost to make many kinds of real-time applications possible [ 1 I . This paper presents a new high-density quaternary logic array chip for high-speed pattern matching instead of depending on expensive and time-consuming software systems 121. A double pattern matching algorithm can be effectively employed for achieving greater densities on smaller semiconductor chips. The appropriate quaternary encoding for the contents of B working memory and a production memory can perform a double pattern matching. Four states for two-bit information concerning with two elements of a rule can be stored into a pattern matching cell using multiple ion implant technique which makes the threshold of the transistor programmable [ 3 ] , A9 a result, the pattern matching cell can be implemented by using only a single transistor. The number. of cells and transistors in the proposed logic array are reduced to 50% of the corresponding binary implementation. Moreover, the pattern matching operations can be performed in parallel, so that the processing time on each reasoning cycle can be provided by the propagation delay time of a single transistor. information processing system interpreters. For